mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 113

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

I
Table 46:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
Parameter/Condition
Operating one bank active-precharge current:
(I
HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
= 0mA; BL = 4, CL = CL (I
(Idd),
CS# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as I
Precharge power-down current: All banks idle;
(I
stable; Data bus inputs are floating
Precharge quiet standby current: All banks idle;
(I
inputs are stable; Data bus inputs are floating
Precharge standby current: All banks idle;
CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are switching; Data bus inputs are switching
Active power-down current: All banks open;
(I
stable; Data bus inputs are floating
Active standby current: All banks open;
t
HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
Operating burst write current: All banks open, continuous
burst writes; BL = 4, CL = CL (I
=
between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All banks open, continuous
burst reads, I
(I
HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
Burst refresh current:
every
valid commands; Other control and address bus inputs are
switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other
control and address bus inputs are floating; Data bus inputs
are floating
DD
RAS =
DD
DD
DD
DD
DD
t
RAS MAX (I
),
); CKE is LOW; Other control and address bus inputs are
); CKE is HIGH, CS# is HIGH; Other control and address bus
); CKE is LOW; Other control and address bus inputs are
),
Specifications and Conditions
t
t
t
t
RC =
RAS =
RAS =
RFC (I
t
RAS MAX (I
t
RC (I
DD
t
OUT
t
RAS MAX (I
DDR2 I
Notes: 1–7; notes appear on page 114
RAS MIN (I
DD
) interval; CKE is HIGH, CS# is HIGH between
DD
),
= 0mA; BL = 4, CL = CL (I
t
),
RP =
DD
t
RAS =
),
DD
t
t
DD
DD
RP =
DD
t
RP (I
CK =
Specifications and Conditions (continued)
), AL = 0;
),
),
t
RAS MIN (I
t
t
DD
RCD =
t
DD
RP =
RP (I
t
CK (I
); CKE is HIGH, CS# is HIGH
), AL = 0;
t
DD
RP (I
DD
DD
t
t
RCD (I
CK =
); CKE is HIGH, CS# is
4W
); refresh command at
DD
DD
DD
t
); CKE is HIGH, CS# is
); CKE is HIGH, CS# is
t
CK =
CK (I
DD
t
), AL = 0;
CK =
); CKE is HIGH,
t
CK =
DD
t
CK (I
t
CK =
t
CK (I
),
t
CK =
t
t
t
t
CK (I
CK =
RC =
t
CK =
DD
CK =
t
DD
CK
),
t
DD
),
t
CK
t
t
RAS
OUT
t
CK
RC
t
CK
CK
113
);
Symbol
I
I
I
I
I
I
I
DD
I
DD
DD
DD
I
I
DD
DD
DD
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
6L
0
1
5
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Configuration
Slow PDN exit
I
Fast PDN exit
DD
MR[12] = 0
MR[12] = 1
x4, x8, x16
x4, x8, x16
2Gb: x4, x8, x16 DDR2 SDRAM
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
Specifications and Conditions
x16
x16
x16
x16
x16
x16
x16
x16
-3E/-3
100
135
145
160
150
250
170
275
280
280
55
65
60
70
40
10
55
75
©2006 Micron Technology, Inc. All rights reserved.
8
8
4
-37E
115
105
135
130
190
150
195
260
260
90
45
45
50
60
35
10
45
55
8
8
4
115
105
135
125
160
140
180
250
250
-5E
90
40
40
45
50
30
10
40
50
8
8
4
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA