mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 36

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 16:
Figure 17:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
BA0, BA1, BA2
COMMAND
ADDRESS
CK#
CK
Bank a
Row
ACT
ACTIVE Command
8-Bank Activate Restriction
T0
t
RRD (MIN)
Note:
Bank a
READ
Col
T1
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to
be issued prior to
command to the internal device by AL clock cycles.
No more than 4-bank ACTIVE commands may be issued in a given
t
DDR2 devices, regardless of the number of banks already open or closed, as shown in
Figure 17.
BANK ADDRESS
RRD.
RRD (MIN) restriction still applies. The
8-bank DDR2-533 (-37E, x4 or x8),
t
ADDRESS
FAW (MIN) = 37.5ns.
Bank b
Row
ACT
T2
RAS#
CAS#
WE#
CK#
CKE
CS#
CK
Bank b
READ
Col
T3
DON’T CARE
Bank
Row
t
RCD (MIN) by delaying the actual registration of the READ/WRITE
Bank c
ACT
Row
T4
36
t
FAW (MIN)
READ
Bank c
Col
T5
t
CK = 3.75ns, BL = 4, AL = 3, CL = 4,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
FAW (MIN) parameters apply to all 8-bank
Bank d
Row
ACT
T6
2Gb: x4, x8, x16 DDR2 SDRAM
Bank d
READ
Col
T7
Bank/Row Activation
NOP
T8
©2006 Micron Technology, Inc. All rights reserved.
t
FAW (MIN) period.
t
RRD (MIN) = 7.5ns,
NOP
T9
Bank e
DON’T CARE
ACT
T10
Row