gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 159

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

15 Appendix B: SFR description
15.1 Port 0 Register (P0)
This port functions as a multiplexed address/data bus during external memory access, and as a general
purpose I/O port on devices which incorporate internal program memory. During external memory cycles,
this port will contain the LSB of the address when ALE is high, and data when ALE is low. When used as
a general purpose I/O, this port is open-drain and can select pull-up resistors optionally. If SFR P0SEL is
set to “1”, writing a 1 to this port will place it in a high impedance mode, which is necessary if the pin is to
be used as an input, and if not, pull-up resistor in port 0 is on. Pull-up resistors are not required when
used as a memory interface.
Only P0.0 can be configurable as analog input (ADC input channel 0).
15.2 Stack Pointer Register (SP)
The stack pointer identifies the location where the stack will begin. The stack pointer is incremented
before every PUSH operation. This register defaults to 07H after reset.
15.3 Data Pointer Low Register (DPL)
This register is the low byte of the 16-bit data pointer. DPL and DPH are used to point to non-scratchpad
data RAM.
Bit No.
Bit No.
Bit No.
80h
81h
82h
MiDAS1.0 Family
R/W(1)
R/W(0)
R/W(0)
DPL.7
P0.7
SP.7
7
7
7
R/W(1)
R/W(0)
R/W(0)
DPL.6
P0.6
SP.6
6
6
6
R/W(1)
R/W(0)
R/W(0)
DPL.5
P0.5
SP.5
5
5
5
R/W(1)
R/W(0)
R/W(0)
DPL.4
P0.4
SP.4
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4
4
4
R/W(1)
R/W(0)
R/W(0)
DPL.3
P0.3
SP.3
3
3
3
R/W(1)
R/W(1)
R/W(0)
DPL.2
P0.2
SP.2
2
2
2
R/W(1)
R/W(1)
R/W(0)
DPL.1
P0.1
SP.1
1
1
1
R/W(1)
R/W(1)
R/W(0)
DPL.0
P0.0
SP.0
0
0
0
DPL
P0
SP