gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 38

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

First the Watchdog timer should be cleared by setting the bit RWT (WDCON.0). Then the timer restarts
from 0. After clearing the Watchdog timer, the hardware clears the RWT bit automatically. The time-out
interval is selected by the values of the two bits WD1 and WD0 (CKCON.7 and CKCON.6). When the
selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set. If the watchdog reset is
enabled by setting the bit EWT to logic 1, the watchdog reset will occur after 512 clock cycles since the
watchdog timer interrupt flag is set, However, the watchdog timer can be cleared by setting the bit RWT
to logic 1 during the delay of 512 clock cycles. Then the watchdog reset will not occur. The reset process
will last for thirty clock cycles, and the Watchdog timer reset flag WTRF (WDCON.2) will be set. This flag
indicates to software that the Watchdog time-out was the cause of the reset.
If the reset and the interrupt are disabled, the watchdog timer can be used as a simple timer. Every time
the selected time-out occurs, the WDIF flag is set. Software can check the WDIF flag to detect a time-out
and set the bit RWT to restart the timer. The Watchdog timer can also be used as a timer with a very long
time-out interval. The interrupt is enabled in this case. Every time the time-out occurs, the interrupt
service routine will be called if the global interrupt enable bit EA is set.
The main purpose of the watchdog timer is detection of software upset. This is important for real-time
control applications. In this case, some power glitches or electro-magnetic interference may cause
software upset.
The watchdog time-out interval varies with the clock frequency. The watchdog timer reset will occur after
512 clocks from the end of the time-out interval.
WDCON.0
RESET
RWT
CLK
0
27-bit Counter
Figure 6-14 Block Diagram for Watchdog Timer
17
20
23
26
2
2
2
2
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26
23
20
17
WD1
CKCON[7:6]
11
10
01
00
WD0
WDCON.3
WDIF
512 clocks
Delay
Functional Description
WDCON.1
WDCON.2
EWDT
WTRF
EWT
EIE.4
Interrupt
WDT Reset