gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 67

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will
execute an internally generated LCALL instruction that will vector the process to the appropriate interrupt
vector address. The conditions for generating the LCALL are
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is repeated
every machine cycle, with the interrupts sampled in the same machine cycle. Note that if an interrupt flag
is active but not being responded to for one of the above conditions, and is not still active when the
blocking condition is removed, the denied interrupt will not be serviced. This means that active interrupts
are not remembered; every polling cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate service
routine. This may or may not clear the flag that caused the interrupt. In case of timer interrupts, the TF0 or
TF1 flags are cleared by hardware whenever the processor vectors to the appropriate timer service
routine. In case of external interrupts, /INT0 and /INT1, the flags are cleared only if they are edge
triggered. In case of UART interrupts, the flags are not cleared by hardware. In the case of Timer 2
interrupt, the flags are not cleared by hardware. Watchdog timer interrupt flag WDIF have to be cleared
by software. The hardware LCALL behaves exactly like the software LCALL instruction. This instruction
saves the Program Counter contents onto the stack, but does not save the PSW. The Program Counter is
reloaded with the vector address of that interrupt which caused the LCALL.
Execution proceeds from the vector address until an RETI instruction is encounter. RETI instruction
informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from
the stack and reloads the Program Counter. Execution of the interrupted program continues from where it
left off. Note that a simple RET instruction would also have returned execution to the interrupted program,
but it would have left the interrupt control system thinking that the service routine was still in progress.
6.2.8.3 Interrupt Response Time
The response time for each interrupt source depends on several factors, such as the nature of the
interrupt and the instruction in progress. The external interrupt inputs, /INT0 to /INT5, are sampled at S3
state of every machine cycle. After that, their interrupt flags IEx will be set. The Timer 0 and 1 overflow
flags are set at S3 state of the machine cycle in which overflow has occurred. These flag values are
polled in the next machine cycle. If a request is active and all three conditions are met, then the hardware
generated LCALL is executed. This LCALL takes four machine cycles to be completed. Thus there is a
1.
2.
3.
Neither an equal priority nor a higher priority interrupt is currently being serviced.
The current polling cycle is the last machine cycle of the instruction currently being executed.
The instruction in progress is neither RETI nor any write to IP, IE, EIP,EIE, IPH or EXIF.
MiDAS1.0 Family
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