gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 97

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

ANL
ANL A, Rn
ANL A, direct
Description:
Operation:
Operation:
Encoding:
Encoding:
<dest-byte>, <src-byte>
Function:
Example:
MiDAS1.0 Family
Cycles:
Cycles:
Bytes:
Bytes:
Logical-AND for byte variables
ANL performs the bitwise logical-AND operation between the variables
indicated and stores the results in the destination variable. No flags are
affected.
The two operands allow six addressing mode combinations. When the
destination is the Accumulator, the source can use register, direct, register,
indirect, or immediate addressing; when the destination is a direct address, the
source can be the Accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value used as
the original port data will be read from the output data latch not the input pins.
If the Accumulator holds 0C3h (11000011b) and register 0 holds 55h
(0101010b) then the instruction,
ANL A, R0
will leave 41h (01000001b) in the Accumulator.
When the destination is a directly addressed byte, this instruction will clear
combinations of bits in any RAM location or hardware register. The mask byte
determining the pattern of bits to be cleared would either be a constant
contained in the instruction or a value computed in the Accumulator at run-time.
The instruction,
ANL P1, # 01110011b
will clear bits 7, 3, and 2 of output port 1.
1
1
ANL
(A)
2
2
ANL
(A)
0
0
←
←
1
1
(A)
(A)
0
0
∧
∧
(Rn)
(direct)
1
1
1
0 1 0 1
r
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r
r
direct address