gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 7

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

MiDAS1.0 Family
Figure 6-8 Configuration of PORT3.............................................................................................................30
Figure 6-9 Configuration of PORT4.............................................................................................................30
Figure 6-10 ESD protection scheme I .........................................................................................................31
Figure 6-11 ESD protection scheme II ........................................................................................................31
Figure 6-12 Power-On Reset/Power-fail Reset and Power-fail interrupt (V
=4.0V and V
=2.5V).........36
PFI
RST
Figure 6-13 LVD Block Diagram..................................................................................................................37
Figure 6-14 Block Diagram for Watchdog Timer .........................................................................................38
Figure 6-15 Timer/Counter 0/1 in Mode 0/1/2/3 ..........................................................................................42
Figure 6-16 Timer/Counter 2 in Capture, Auto reload, and Clock-out Mode ..............................................44
Figure 6-17 Timer/Counter 2 in Baud Rate Generator Mode......................................................................45
Figure 6-18 UART Mode 0 ..........................................................................................................................47
Figure 6-19 UART Mode 0 Timing ..............................................................................................................48
Figure 6-20 UART Mode 1 ..........................................................................................................................49
Figure 6-21 UART Mode 1 Timing ..............................................................................................................50
Figure 6-22 UART Mode 2 ..........................................................................................................................51
Figure 6-23 UART Mode 2 Timing ..............................................................................................................52
Figure 6-24 UART Mode 3 ..........................................................................................................................53
Figure 6-25 UART Mode 3 Timing ..............................................................................................................54
Figure 6-26 Functional block diagram .........................................................................................................56
Figure 6-27 In 8bit counter mode, PWM basic timing diagram ...................................................................59
Figure 6-28 In 2+6bit count mode, PWM basic timing diagram ..................................................................60
Figure 6-29 In 2+6bit counter mode, PWM extension cycle timing diagram...............................................60
Figure 6-30 Analog-to-Digital Converter block Diagram .............................................................................62
Figure 6-31 A/D Converter Timing Diagram................................................................................................64
Figure 6-32 Interrupt Vector Generation Flow.............................................................................................65
Figure 6-33 Hierarchy of Interrupt Priority ...................................................................................................66
Figure 6-34 Three Reset Resources ...........................................................................................................68
Figure 6-35 Configuration for Clock Generators .........................................................................................70
Figure 6-36 Clock Circuit .............................................................................................................................71
Figure 6-37 The Load Capacitor vs. Operating Frequency.........................................................................71
Figure 6-38 Power Management Circuit......................................................................................................72
Figure 6-39 The EPROM Cell Configuration In Physical Layout.................................................................74
Figure 6-40 Pin Configuration for EPROM programming............................................................................75
Figure 6-41 Timing of EPROM programming and Verification....................................................................76
Figure 7-1 Noise reduction ..........................................................................................................................77
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