gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 48

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

6.2.5.2 Mode 1
In Mode 1, the UART communicates asynchronously in the full duplex. Ten bits are transmitted (through
TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receiving,
the stop bit goes into RB8 in the SCON. The baud rate can be programmed to be 1/16 or 1/32 of the
Timer 1 overflow or 1/16 of the Timer 2 overflow rate. It varies widely according to the automatic reload
value of Timer 1 or Timer 2.
Transmission is initiated by any instruction that uses SBUF as a destination register. The serial data is
sent to TxD pin at S1 state after the first roll-over of the divide-by-16 counter. The next bit is placed on
TxD pin at S1 state after the next roll-over of the divide-by-16 counter. Thus, the transmission is
synchronized to the divide-by-16 counter, not directly to the “write to SBUF” signal. After transmission of
all 8-bit data, the stop bit is transmitted. The TI flag is set in the S1 state after the stop bit has been sent
to TxD pin. This will occur at the 10
Reception is enabled only if REN is “1”. It is initiated by detecting 1-to-0 transition at RxD. For this
purpose RxD is sampled at a rate of 16 times whatever baud rate established. When a transition is
detected, the divide-by-16 counter is immediately reset. This aligns its roll-overs with the boundaries of
the incoming bit times.
The 16 states of the counter divide each bit time into 16 ths. At the 8
[Transmit]
[Receive]
TXD (Shift Clock)
TXD (Shift Clock)
RXD (Data Out)
RXD (Data Out)
Write to SCON
Write to SBUF
(Clear RI)
Receive
SEND
Shift
Shift
ALE
RI
TI
S4
S1 S2 S3 S4 S1 S2 S3 S4 S1 S2 S3 S4 S1 S2 S3 S4 S1 S2 S3 S4 S1 S2 S3 S4 S1 S2 S3 S4 S1 S2 S3 S4 S1 S2 S3 S4 S1 S2 S3 S4
Figure 6-19 UART Mode 0 Timing
th
S2
D0
roll-over of the divide-by-16 counter after a write to SBUF.
S4
D0
D1
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D1
D2
D2
D3
D3
D4
D4
th
D5
Functional Description
, 9
th
D5
, and 10
D6
D6
th
D7
counter states of each
D7
S1