gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 69

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

MiDAS1.0 Family
6.2.9.1 Power On/Fail Reset
The MiDAS1.0 family has a precision band-gap voltage reference to recognize that V
is out of tolerance.
CC
When power is turned on, its internal circuit detects the rise of V
above V
, the reset threshold (2.5V)
CC
RST
voltage. Once V
is above this voltage, its oscillator starts oscillation. Then its internal reset circuit waits
CC
for 65,536 clock cycles until the power supply and the oscillator are stabilized. Next, the MiDAS1.0
processor will exit the reset state. No external components are needed to generate a power on reset.
During power-down or during a severe power glitch, if V
falls below V
, the processor will also set
CC
RST
Power On Reset flag to high. The reset state is maintained as long as the power voltage remains below
the threshold. This will occur automatically, needing no action from the user or from the software.
6.2.9.2 External Reset
The reset input is the RST pin. The external input signal is asynchronous to the internal clock. The RST
pin is sampled during state S4 of every machine cycle. The RST pin must be held for at least 6 machine
cycles (24 clocks) to accomplish an external reset. The reset circuitry synchronously generates the
internal reset signal. Thus the reset procedure operates synchronously, while the clock is running.
Once the device is in reset state, it will remain so as long as RST is 1. Even after RST is deactivated, the
device will continue to be in reset state for up to three machine cycles, and then begin program execution
from 0000h. There is no flag associated with the external reset condition. However, since the other two
reset sources have flags, the external reset can be considered as the default reset if those two flags are
cleared.
6.2.9.3 Watchdog Timer Reset
The Watchdog timer is a free running timer with programmable time-out intervals. The user can clear the
watchdog timer at any time, causing it to restart the count. When the time-out interval is reached, an
interrupt flag is set. If the Watchdog timer reset is enabled and the Watchdog timer is not cleared, then
512 clocks from the flag being set, the Watchdog timer will generate a reset. This reset condition is
maintained by hardware for thirty clock cycles. Once the reset is removed the device will begin execution
from 0000h.
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