tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 131
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tmp1940cyaf
Manufacturer Part Number
tmp1940cyaf
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP1940CYAF.pdf
(464 pages)
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BEXCS
(0xFFFF_E488)
9.3
Application Example
128 Kbytes of ROM and 256 Kbytes of RAM are connected off-chip through a 16-bit data bus.
pins. To use them as chip select pins, set appropriate bits in the Port 4 Control (P4CR) register and the Port 4
Function (P4FC) register to 1.
TMP1940CYAF
Figure 9.7 External Memory Connections (ROM Width = 16 bits, RAM Width = 16 bits)
Figure 9.7 shows an example usage of the TMP1940CYAF programmable chip selects. In this example,
Both CS1 and CS2 are shared with Port 4 pins. Upon reset, all Port 4 pins are configured as input port
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
AD8–15
A16–17
AD0–7
HWR
BW1
BW0
CS2
ALE
CS1
WR
RD
Chip select output
waveform
00: ROM/RAM
Don’t use any other
value.
BEXOM
W
0
Figure 9.6 Chip Select/Wait Control Registers
15
7
Latch
D Q
LE
0
16
14
6
TMP1940CYAF-89
A1–15
A1–15
13
5
A16
A1–15
A16–17
A16–17
Data bus
width
0: 16-bit
1: 8-bit
BEXBUS
W
0
12
4
ROM (128 Kbits
RAM (128 Kbits
RAM (128 Kbits
OE
CE
OE
R/
CE1
OE
R/
CE1
A15
A0–14
A15–16
A0–14
A15–16
A0–14
W
W
Sets the number of Wait cycles
0000–0111: 0–7 wait states
1111: (1
Don’t use any other value.
BEXW
0
Upper Byte
Lower Byte
11
3
WAIT pin
N) wait states, as determined by the
8)
8)
16)
1
TMP1940CYAF
10
2
I/O1–8
I/O1–8
D8–15
D0–7
Number of dummy
cycles (Read recovery
time)
00: 2 dummy cycles
01: 1 dummy cycle
10: No dummy cycle
11: Don’t use.
0
BEXRCV
W
0
1
9
1
0
0
8
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