tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 251

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.5.11 Slave Address Match Monitor
14.5.12 General-Call Detection Monitor
14.5.13 Last Received Bit Monitor
Master
Master
SCL clock. The master loses arbitration if there is a difference between these two values. The losing
master sets the AL bit in the SBI0SR to 1, which causes the MST and TRX bits in the same register to
be cleared. That is, the losing master switches to slave-receiver mode.
SBI0CR2 is programmed with new parameters.
A
B
the incoming slave address or not. In Address Recognition mode (i.e., ALS=0), the Addressed-As-Slave
(AAS) bit in the SBI0SR is set when an incoming address over the I
I2C0CR or when the general-call address has been received. When ALS=1, the AAS bit is set when the
first data word has been received. The AAS bit is cleared each time the SBI0DBR is read or written.
been received. The general-call address is detected when the eight bits following a START condition
are all zeros. The AD0 bit is cleared when a START or STOP condition is detected on the bus.
edge of the SCL clock. In Acknowledge mode, reading this bit immediately after generation of the
INTS2 interrupt returns the value of the ACK signal.
A master compares its internal data level to the actual level on the SDA line at the rising edge of the
The AL bit is subsequently cleared when data is written to or read from the SBI0DBR and when the
When acting as a slave-receiver, the ALS bit in the I2C0CR determines whether the SBI recognizes
When acting as a slave receiver, the AD0 bit in the SBI0SR is set when a general-call address has
The LRB bit in the SBI0SR holds the value of the last bit received over the SDA line at the rising
Internal SCL
Level
Internal SDA
Level
Internal SCL
Level
Internal SDA
Level
AL
MST
TRX
Access to the SBI0DBR
or SBI0CR2
Figure 14.12 Master B Loses Arbitration (D7A – D7B, D6A – D6B)
D7A
D7B
1
1
D6A
D6B
TMP1940CYAF-209
2
2
D5A D4A D3A D2A D1A D0A
3
3
Internal SDA level is held high
because Master B has lost arbitration.
4
4
5
Clock output stops here
6
7
8
2
C bus matches the value in the
TMP1940CYAF
9
D7A’ D6A’ D5A’ D4A’
1
2
3
4