tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 51

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.
3.1
Core Processor
description of the core processor, refer to the 32-Bit TX System RISC TX19 Core Architecture manual.
below.
The TMP1940CYAF contains a high-performance 32-bit core processor called the TX19. For a detailed
Functions unique to the TMP1940CYAF, which are not covered in the architecture manual, are described
Reset Operation
power supply voltage and the internal high-frequency oscillator have stabilized. This time is typically 3 s at
32 MHz when the on-chip PLL is utilized, and 6 s otherwise. After a reset, either the PLL-multiplied clock
or an external clock is selected, depending on the logic state of the PLLOFF pin. By default, the selected
clock is geared down to 1/8 for internal operation.
Note: A reset operation does not affect the contents of the on-chip RAM.
To reset the TMP1940CYAF, RESET must be asserted for at least 12 system clock periods after the
The following occurs as a result of a reset:
The System Control Coprocessor (CP0) registers within the TX19 core processor are initialized.
For details, refer to the 32-Bit TX System RISC TX19 Core Architecture manual.
The Reset exception is taken. Program control is transferred to the exception handler at a
predefined address. This predefined location is called exception vector, which directly indicates the
start of the actual exception handler routine. The Reset exception is always vectored to virtual
address 0xBFC0_0000 (which is the same as for the Nonmaskable Interrupt exception).
All on-chip I/O peripheral registers are initialized.
All port pins, including those multiplexed with on-chip peripheral functions, are configured as
either general-purpose inputs or general-purpose outputs.
TMP1940CYAF-9
TMP1940CYAF