tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 257
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tmp1940cyaf
Manufacturer Part Number
tmp1940cyaf
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP1940CYAF.pdf
(464 pages)
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(2) Slave Mode (SBI0CR2.MST = 0)
Example: When the received slave address matches the SBI’s own address and the data direction
generates the INTS2 interrupt on four occasions: 1) when the SBI has received any slave address;
2) when the SBI has received a general-call address; 3) when the received slave address matches its
own address in the I2C0AR; and 4) when a data transfer has been completed in response to a
general-call.
arbitration is lost during a data transfer, SCL continues to be generated until the data word is
complete; then the INTS2 interrupt is generated.
pulled low. When the SBI0DBR is read or written or when the PIN bit is set back to 1, the SCL
line is released after a period of t
over to slave mode as a result of lost arbitration.
summarized in Table 14.2.
X = Don’t care
INTS2 interrupt
if TRX = 0
Then go to other processing
if AL = 1
Then go to other processing
if AAS = 0
Then go to other processing
SBI0CR1
SBI0DBR
If the MST bit in the SBI0CR2 is cleared, the SBI is in slave mode. In slave mode, the SBI
Also, if the SBI, as a master, loses arbitration for the I
When the INTS2 interrupt occurs, the PIN bit in the SBI0SR is cleared, and the SCL line is
Processing to be done in slave mode varies, depending on whether or not the SBI has switched
Test the AL, TRX, AAS and AD0 bits in the SBI0SR to determine the processing required, as
(
/ R
W
) bit is 1
X X X 1 0 X X X
X X X X 0 X X X
TMP1940CYAF-215
LOW
.
Set the number of bits to be transmitted.
Load the transmit data.
2
C bus, it switches to slave mode. If
TMP1940CYAF
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