tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 133

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.2 Implementation
10.2.1
† Internal signals
On-Chip DMAC Interface
Interrupt Controller (INTC).
two associated signals: a DMA request (INTDREQn) and a DMA acknowledge ( DACKn ), where n is
a channel number from 0 to 3. INTDREQn is an input to the DMAC coming from the INTC, and
DACKn is an output signal from the DMAC going to the INTC.
processor grants the processor data bus to the DMAC, so that the DMAC can access the on-chip RAM
and ROM connected to the processor. Snooping can be enabled and disabled under software control.
The DMAC bus snooping is discussed in the next subsection in more details.
GREQ. GREQ is a bus request without snooping. SREQ is a bus request with snooping.
Bus Grant Ackowledge
Note: DMA channel priority exists only among those using the same type of bus request signal (SREQ
Bus Release Request
Figure 10.1 shows how the DMAC is internally connected with the TX19 core processor and the
The DMAC provides four independently programmable channels. With each DMA channel, there are
Channel priority is fixed. Channel 0 has the highest priority, and Channel 3 has the lowest priority.
The TX19 core processor supports bus snooping. When snooping is enabled, the TX19 core
There are two bus request signals from the DMAC going to the TX19 core processor, SREQ and
Core Processor
TX19
or GREQ). For example, once a given DMA channel has acquired bus mastership using SREQ, no
other DMA channel can assume bus mastership using GREQ until the ongoing DMA transaction is
completed.
Bus Request
Figure 10.1 DMAC Connections within the TMP1940CYAF
Bus Grant
Address
Control
Data
TMP1940CYAF-91
INTDREQ[3:0] †
DMAC
DACK
[
: 3
] 0
†
BUSGNT †
Controller
Interrupt
(INTC)
TMP1940CYAF
External Interrupt
Requests
On-Chip I/O Peripheral
Interrupt Requests†
BUSREQ †
BUSREL †
HAVEIT †