tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 249

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.5.6
14.5.7
SDA Line
SCL Line
START Condition
Configuring the SBI as a Transmitter or a Receiver
receiver.
of the data direction (
TRX bit reflects the value of the
an acknowledge from an addressed slave. The TRX bit changes to the opposite value of the
sent by the SBI. If the SBI does not receive an acknowledge from a slave, the TRX bit retains the
previous value.
for the I
Generating START and STOP Conditions
and PIN bits in the SBI0CR2 causes the SBI to generate a START condition on the bus and shift out 8-
bit I
and PIN bits and a 0 to the BB bit causes the SBI to start a sequence for generating a STOP condition
on the bus to abort the transfer. The MST, TRX, BB and PIN bits should not be altered until a STOP
condition appears on the bus.
condition is detected and cleared when a STOP condition is detected.
The SBI0CR2.TRX bit is set or cleared by hardware to configure the SBI as a transmitter or a
As a slave, the SBI is put in either slave-receiver or slave-transmitter mode, depending on the value
As a master, the SBI is put in either master-transmitter or a master-receiver mode upon reception of
The TRX bit is cleared by hardware when a STOP condition has been detected and when arbitration
When the SBI0SR.BB bit is cleared, the bus is free. At this time, writing 1s to the MST, TRX, BB
When the SBI0SR.BB bit is set, the bus is busy. When SBI0SR.BB=1, writing 1s to the MST, TRX
The BB bit can be read to determine if the I
2
when transferring data using addressing format
when the received slave address matches the value in I2C0CR
when a general-call address is received; i.e., the eight bits following the START condition are all
zeros.
C-bus data. Before generating a START condition, the ACK bit must be set to 1.
2
Figure 14.9 Generating a START Condition and a Slave Address
C bus has been lost.
A6
1
Figure 14.10 Generating a STOP Condition
SDA Line
SCL Line
/ R
W
A5
2
) bit transmitted by the master. When the SBI is addressed as a slave, the
TMP1940CYAF-207
/ R
A4
W
Slave Address and Direction bit
3
bit. The TRX bit is set or cleared on the following occasions:
A3
STOP Condition
4
2
C bus is in use. The BB bit is set when a START
A2
5
A1
6
A0
7
TMP1940CYAF
R/W
8
Acknowledge Signal
9
/ R
W
bit