tmp1940cyaf TOSHIBA Semiconductor CORPORATION, tmp1940cyaf Datasheet - Page 61

• Manufacturer Part Number: tmp1940cyaf
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.3
5.3.1
System Clock Control Section
SYSCR1.GEAR[1:0] bits to 00, putting the TMP1940CYAF in Single-Clock mode. If the on-chip PLL is
enabled, the PLL reference clock is always multiplied by four. By default, the system clock frequency (fsys)
is geared down to fc/8, where fc = fosc
crystal is connected between the X1 and X2 pins, the fsys clock operates at 4 MHz (8
logic state of the PLLOFF pin, the fsys frequency is, by default, geared down to fc/8. A reset clears the
SYSCR1.DFOSC bit to 0, setting fc to fosc/2. Therefore, for example, if a 20-MHz crystal is connected
between the X1 and X2 pins, fsys becomes 20
cycle, it is recommended to use the default DFOSC bit value of 0 (i.e., fc = fosc
by-2 clock generator may be bypassed by setting the DFOSC bit after reset. This causes fc to be equal to
fosc; i.e., fsys becomes double the rate available when a crystal is connected between X1 and X2.
A system reset initializes the SYSCR0.XEN bit to 1, the SYSCR0.XTEN bit to 0 and the
The PLL output clock can be disabled by setting the PLLOFF pin low during reset. Regardless of the
Alternatively, the X1 pin can be driven with an external clock. Since the fsys clock must have a 50% duty
Oscillation Stabilization Time When Switching Between NORMAL and SLOW Modes
integrated warm-up period timer is used to assure oscillation stability. The warm-up period can be
selected through the WUPT1–WUPT0 bits of the SYSCR2 to suit the crystal used. The warm-up period
timer can be started by software writing a 1 to the WUEF bit in the SYSCR0. This bit is self-clearing; it
can be read to ascertain that the timer has expired.
SLOW modes.
Assumption: fosc = 8 MHz, fs = 32.768 kHz
Note 1:
Note 2:
Note 3:
Note 4:
When a crystal is connected between the X1 and X2 pins and/or the XT1 and XT2 pins, the
Table 5.1 shows the warm-up periods required when the clocking is switched between NORMAL and
Warm-up Period Select
10 (2
11 (2
01 (2
SYSCR2.WUPT[1:0]
No warm-up is necessary when the TMP1940CYAF is driven by an external oscillator clock which
is already stable.
Because the warm-up period timer is clocked by the oscillator clock, any frequency fluctuations
will lead to small timer errors. Table 5.1 should be considered as approximate values.
Ensure that the PLL lock flag (SYSCR3.LUPFG) is cleared before starting the warm-up period
timer.
When a low-speed crystal is connected between XT1 (Port 96) and XT2 (Port 97), the following
register settings are required to reduce power consumption:
When a crystal is connected between XT1 and XT2:
When XT1 is driven with an external clock:
14
16
8
/ oscillation frequency)
/ oscillation frequency)
/ oscillation frequency)
P9CR.P96C–P97C = 11
P9.P96–P97 = 00
P9CR.P96C–P97C = 11
P9.P96–P97 = 10
Table 5.1 Warm-up Periods
TMP1940CYAF-19
4 (fosc is the oscillator frequency). For example, if an 8-MHz
High-Speed Clock
1/2
32
2.048 (ms)
8.192 (ms)
(fosc)
1/8 = 1.25 MHz.
( s)
Low-Speed Clock
TMP1940CYAF
7.8
500
2000 (ms)
(fs)
1/2). However, the divide-
(ms)
(ms)
4
1/8).