lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet
lrs1383
Available stocks
Related parts for lrs1383
lrs1383 Summary of contents
Page 1
...
Page 2
Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
Page 3
Description ...
Page 4
... Description The LRS1383 is a combination memory organized as 2,097,152 x16 bit flash memory and 524.288 x16 bit static RAM in one package. Features - Power supply - Operating temperature - Not designed or rated as radiation hardened - 72pin CSP (LCSP072-P-0811) plastic package - Flash memory has P-type bulk silicon, and SRAM has P-type bulk silicon ...
Page 5
Pin Configuration INDEX (TOP View) 3 ...
Page 6
Pin Address Inputs (Common F Address Inputs (Flash) F S-A Address Input (SRAM) 17 F-CE Chip Enable Inputs (Flash) S-CE , S-CE Chip Enable Inputs (SRAM) ...
Page 7
Truth Table (1) 3.1 Bus operation F-CE Flash SRAM Notes Read 3,5 Output 5 Standby Disable Write 2,3,4,5 Read 5 Output Standby 5 Disable Write 5 Read 5,6 Reset Power Output 5,6 Down Disable Write 5,6 Standby 5 Standby ...
Page 8
Simultaneous Operation Modes Allowed with Four Planes IF ONE Read Read PARTITION IS: Array ID/OTP Read Array X X Read ID/OTP X X Read Status X X Read Query X X Word Program X X Page Buffer X X ...
Page 9
Block Diagram ...
Page 10
Command Definitions for Flash Memory 5.1 Command Definitions Command Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block ...
Page 11
Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. 7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid address ...
Page 12
Identifier Codes and OTP Address for Read Operation Manufacturer Code Device Code Block Lock Configuration Code Device Configuration Code OTP Notes: 1. The address read the manufacturer, device, lock configuration, device configuration code and OTP data ...
Page 13
OTP Block Address Map (1) 5.5 Functions of Block Lock and Block Lock-Down State F- [000 (4) [001] [011 [100 ( [101] ( [110] [111] ...
Page 14
Block Locking State Transitions upon Command Write Current State DQ DQ State F-WP 1 [000 [001 [011 [100 [101 [110 [111 Note: 1. "Set Lock" ...
Page 15
Status Register Definition WSMS BESS BEFCES 7 6 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND ...
Page 16
SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS ...
Page 17
PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1-3 are merged into one partition. (default in a ...
Page 18
Memory Map for Flash Memory ...
Page 19
Absolute Maximum Ratings Symbol Parameter V Supply voltage CC V Input voltage IN T Operating temperature A T Storage temperature STG F-V F-V voltage PP PP Notes: 1. The maximum applicable voltage on any pins with respect to GND. ...
Page 20
DC Electrical Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current LO I F-V Standby Current CCS CC F-V Automatic Power Savings CC I CCAS Current I F-V Reset Power-Down Current CCD CC Average F-V ...
Page 21
Symbol Parameter I S-V Standby Current S-V Standby Current SB1 CC I S-V Operation Current CC1 CC I S-V Operation Current CC2 CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage ...
Page 22
AC Electrical Characteristics for Flash Memory 12.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load 12.2 Read Cycle Symbol t Read Cycle Time AVAV t Address to Output ...
Page 23
Write Cycle (F-WE / F-CE Controlled) Symbol F-RST High Recovery to F-WE (F-CE) Going Low PHWL PHEL F-CE (F-WE) Setup to F-WE (F-CE) Going Low ELWL WLEL F-WE (F-CE) Pulse ...
Page 24
Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance Symbol Parameter 4K-Word Parameter Block t WPB Program Time 32K-Word Main Block t WMB Program Time t / WHQV1 Word Program Time t EHQV1 t / WHOV1 ...
Page 25
Flash Memory AC Characteristics Timing Chart AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code ...
Page 26
AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks ...
Page 27
AC Waveform for Write Operations(F-WE / F-CE Controlled ...
Page 28
Reset Operations Symbol F-RST Low to Reset during Read t PLPH (F-RST should be low during power-up.) t F-RST Low to Reset during Erase or Program PLRH t F-V 2.7V to F-RST High VPH CC t F-V 2.7V ...
Page 29
AC Electrical Characteristics for SRAM 13.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load Note: 1. Including scope and socket capacitance. 13.2 Read Cycle Symbol t Read Cycle ...
Page 30
Write Cycle Symbol t Write cycle time WC t Chip enable to end of write CW t Address valid to end of write AW t Byte select time BW t Address setup time AS t Write pulse width WP ...
Page 31
SRAM AC Characteristics Timing Chart Read Cycle Timing Chart ...
Page 32
Write Cycle Timing Chart (S-WE Controlled ...
Page 33
Write Cycle Timing Chart (S-CE Controlled ...
Page 34
Write Cycle Timing Chart (S-UB, S-LB Controlled ...
Page 35
Data Retention Characteristics for SRAM Symbol Parameter V Data Retention Supply voltage CCDR I Data Retention Supply current CCDR t Chip enable setup time CDR t Chip enable hold time R Notes 1. Reference value 25°C, ...
Page 36
Notes This product is a stacked CSP package that a 32M (x16) bit Flash Memory and a 8M (x16) bit SRAM are assembled into. - Supply Power Maximum difference (between F-V - Power Supply and Chip Enable of Flash ...
Page 37
Flash Memory Data Protection Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto F-WE signal or power supply, may be interpreted as ...
Page 38
Design Considerations 1. Power Supply Decoupling To avoid a bad effect to the system by flash memory power switching characteristics, each device should have a 0.1µF ceramic capacitor connected between its F-V Low inductance capacitors should be placed as ...
Page 39
...
Page 40
A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
Page 41
A-1.1.1 Rise and Fall Time Symbol t F-V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
Page 42
A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). See the “DC Electrical Characteristics“ described in specifications for V (Min.) ...
Page 43
A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric ...
Page 44
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all ...
Page 45
... Page Mode Dual Work Flash Memory 32M-bit, 64M-bit LH28F320BX, LH28F640BX Series Appendix Appendix to Spec No.: MFM2-J13207 APPENDIX No. ISSUE: Jan. Model No.: LRS1383 March 1, 2001 18, 2001 Rev. A ...
Page 46
... Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. Please direct all queries regarding the products covered herein to a sales representative of the company. Appendix to Spec No.: MFM2-J13207 FUM00701 Model No.: LRS1383 March 1, 2001 Rev. 2.20 ...
Page 47
... High Performance Read Mode........................ 60 5.4.1 CPU Compatibility................................... 60 5.4.2 Features of ADV# and CLK .................... 60 5.4.3 Address Latch .......................................... 60 5.4.4 Using Asynchronous Page Mode............. 60 5.4.5 Using Synchronous Burst Mode .............. 61 5.4.6 Using WAIT# in Burst Mode................... 61 5.4.7 Single Read Mode.................................... 61 6 Common Flash Interface........................................ 67 7 Related Document Information.............................. 68 Model No.: LRS1383 March 1, 2001 1 PAGE Rev. 2.20 ...
Page 48
... Set Read Configuration Register command. CLK is then used to increment the internal burst address generator, synchronize with the host, and deliver data every clock cycle. The WAIT# output pin is used to signal Model No.: LRS1383 Contains the Blocks within the following Address 32M bit ...
Page 49
... PP (Note 1) Please note following: • For the lockout voltage V functions, refer to specifications. • read operations to protect the data in all blocks. Model No.: LRS1383 AVQV , reset mode is enabled IL level to protect the data from IL to inhibit all write PPLK should be kept lower than V ...
Page 50
... Program Program Model No.: LRS1383 (1, 2) OTP Block Full Chip Program Program Erase Erase Suspend March 1, 2001 4 Block Erase Suspend Rev ...
Page 51
... FUM00701 Figure 1. Block Diagram Synchronous burst mode will be available for future device. Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001 5 Rev. 2.20 ...
Page 52
... RST# resets internal automation and inhibits write operations IL , locked-down blocks cannot be unlocked. Erase IL , lock-down is disabled during a burst mode, data is valid. WAIT# low ( internal resister. The WAIT# signals of the OH Model No.: LRS1383 March 1, 2001 enables normal operation. After ...
Page 53
... V , block erase, full chip erase, (page buffer) program or OTP program PP PPLK provides fast erasing or fast programming mode. In this PP is power supply pin. Applying 12V±0. Model No.: LRS1383 is not used for power supply pin. PP during erase/program can PP may be connected all write attempts to ...
Page 54
... OTP block. Page buffer program operations are available for the main array. OTP program cannot be suspended through the (Page Buffer) Program Suspend command (described later). Dual work operation cannot be executed during OTP program. Model No.: LRS1383 in SHARP factory. This factory Rev ...
Page 55
... FUM00701 Figure 2.1. Memory Map for LH28F320BX series (Top Parameter) Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Rev. 2.20 March 1, 2001 9 ...
Page 56
... FUM00701 Figure 2.2. Memory Map for LH28F320BX series (Bottom Parameter) Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001 10 Rev. 2.20 ...
Page 57
... FUM00701 Figure 3.1. Memory Map for LH28F640BX series (Top Parameter) Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Rev. 2.20 March 1, 2001 11 ...
Page 58
... FUM00701 Figure 3.2. Memory Map for LH28F640BX series (Bottom Parameter) Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001 12 Rev. 2.20 ...
Page 59
... Figure 4. OTP Block Address Map for OTP Program (The area outside 80H~88H cannot be used.) NOTES not used for 32M-bit device Refer to Table 6 through Table the OTP block address map for read operation. Appendix to Spec No.: MFM2-J13207 (1, 2) Model No.: LRS1383 March 1, 2001 13 Rev. 2.20 ...
Page 60
... OTP program, and block lock configuration provides the data protection at the software level against data alternation. Model No.: LRS1383 Because the LH28F320BX/LH28F640BX ), or if the voltage on the IL pin is below the write lock out voltage (V ...
Page 61
... RESET# signal that resets the system CPU. After return from reset mode, the LH28F320BX/ LH28F640BX series is automatically set to asynchronous read mode in which 8-word page mode is available. Delay time t valid. Model No.: LRS1383 ) places the LH28F320BX/ IH during block erase, full chip erase, (page IH for a minimum t ...
Page 62
... CUI always requires the word address, block address or partition address. Before writing the Block Erase command, Full Chip Erase command, (Page Buffer) Program command or OTP Program command, WSM (Write State Machine) should be ready and not be used in any partition. Model No.: LRS1383 Address 0-15 ...
Page 63
... CUI and the address and data are latched on the rising edge of CE# or WE#, whichever goes high first. The command can be written to the CUI at the standard microprocessor writing timing. Appendix to Spec No.: MFM2-J13207 FUM00701 and PPH1/2 requires appropriate (valid), the IL Model No.: LRS1383 Rev. 2.20 March 1, 2001 17 ...
Page 64
... Table 6 through Table 8). Asynchronous page mode and synchronous burst mode are not available for reading identifier codes/OTP. Read operations for identifier codes or OTP block support single asynchronous read cycle or single synchronous read cycle. Model No.: LRS1383 18 voltage and RST# must Rev. 2.20 March 1, 2001 ...
Page 65
... Write BA 2 2,10 Write Write BA 2 2,3,9 Write OA 2 2,3 Write RCRC 2 2,3 Write PCRC - Model No.: LRS1383 (11) Second Bus Cycle (3) (1) (2) Data Oper Addr FFH 90H Read 98H Read QA 70H Read PA 50H 20H Write BA 30H Write X 40H or Write WA 10H ...
Page 66
... Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP WP lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. IH 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. Appendix to Spec No.: MFM2-J13207 FUM00701 Model No.: LRS1383 March 1, 2001 20 . When IL Rev. 2.20 ...
Page 67
... Address (32M-bit device PCR 00H 1 00H or 08H 0 00H or 10H 0 00H or 18H 1 00H or 08H or 10H 0 00H or 10H or 18H 1 00H or 08H or 18H 1 00H or 08H or 10H or 18H Model No.: LRS1383 March 1, 2001 21 Data Notes (1) [DQ - 00B0H 00B4H 2 00B5H 3 00B0H 2 00B1H ...
Page 68
... Identifier Codes/OTP command (90H). Appendix to Spec No.: MFM2-J13207 FUM00701 Address (64M-bit device PCR 00H 1 00H or 10H 0 00H or 20H 0 00H or 30H 1 00H or 10H or 20H 0 00H or 20H or 30H 1 00H or 10H or 30H 1 00H or 10H or 20H or 30H Model No.: LRS1383 (1) for 64M-bit device ] 16 Rev. 2.20 March 1, 2001 22 ...
Page 69
... This command clears only the status register of the addressed partition. During block erase suspend or (page buffer) program suspend, the Clear Status Register command is invalid and the status register cannot be cleared. voltage and PP Model No.: LRS1383 . To clear the status register, write IH error conditions occurring after ...
Page 70
... Reading the block lock configuration codes after writing the Read Identifier Codes/OTP command indicates block lock bit status. SR.15 - SR.8 and SR.0 are reserved for future use and should be masked out when polling the status register. Model No.: LRS1383 ...
Page 71
... XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not. XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status register. Model No.: LRS1383 ...
Page 72
... Dual work operation is not available during the full chip erase mode. The memory array data cannot be read in this mode. To return to the read array mode, write the Read Array command (FFH) to the CUI after the completion of the full chip erase operation. Model No.: LRS1383 through the erase suspend ...
Page 73
... FUM00701 Figure 5.1. Automated Block Erase Flowchart Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Bus Command Operation <First cycle> Data=20H Addr=Within Block to be Erased Write Block Erase <Second cycle> Data=D0H Addr=Within Block to be Erased Status Register Data Read Addr=Within Block to be Erased Check SR.7 Standby ...
Page 74
... FUM00701 Figure 5.2. Automated Block Erase Flowchart (Continued) Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Bus Command Operation Check SR.3 Standby 1=V Error Detect PP Check SR.1 Standby 1=Device Protect Detect Block lock bit is set. Check SR.4,5 Standby Both 1=Command Sequence Error Check SR.5 Standby 1=Block Erase Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked ...
Page 75
... FUM00701 Figure 6.1. Automated Full Chip Erase Flowchart Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Bus Command Operation <First cycle> Data=30H Addr=X Full Chip Write Erase <Second cycle> Data=D0H Addr=X Status Register Data Read Addr=X Check SR.7 Standby 1=WSM Ready 0=WSM Busy Check the status after full chip erase. ...
Page 76
... FUM00701 Figure 6.2. Automated Full Chip Erase Flowchart (Continued) Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Bus Command Operation Check SR.3 Standby 1=V Error Detect PP Check SR.1 Standby 1=Device Protect Detect All Blocks are locked. Check SR.4,5 Standby Both 1=Command Sequence Error Check SR.5 Standby 1=Full Chip Erase Error SR ...
Page 77
... SR.5 and SR.4 of the partition are set to "1". When the data are transferred from the page buffer to the flash array, the status register bit SR.7 is set to "0". Then, the target partition is in the page buffer program busy mode. Model No.: LRS1383 - the start address also correspond 0 3 Rev ...
Page 78
... The array data can be read from partitions not being programmed. Page buffer program operation may occur in only one partition at a time. Other partitions must be in one of the read modes. Appendix to Spec No.: MFM2-J13207 FUM00701 the PP Model No.: LRS1383 Rev. 2.20 March 1, 2001 32 ...
Page 79
... FUM00701 Figure 7.1. Automated Program Flowchart Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Bus Command Operation <First cycle> Data=40H or 10H Addr=Location to be Programmed Word Write <Second cycle> Program Data= Data to be Programmed Addr=Location to be Programmed Status Register Data Read Addr=Location to be Programmed Check SR.7 Standby ...
Page 80
... FUM00701 Figure 7.2. Automated Program Flowchart (Continued) Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Bus Command Operation Check SR.3 Standby 1=V Error Detect PP Check SR.1 Standby 1=Device Protect Detect Block lock bit is set. Check SR.4 Standby 1=Word Program Error SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple locations are programmed before full status is checked ...
Page 81
... FUM00701 Figure 8.1. Automated Page Buffer Program Flowchart Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Bus Command Operation <First cycle> Page Buffer Write Data=E8H Program Addr=Start Address Extended Status Register Read Data Check XSR.7 1=Page Buffer Program Standby Ready 0=Page Buffer Program Busy <Second cycle> ...
Page 82
... Buffer Program Error SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are programmed before full status is checked error is detected, clear the Status Register before attempting retry or other error recovery. Model No.: LRS1383 March 1, 2001 36 Comments Comments Error Detect ...
Page 83
... If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than t and its sequence is repeated, the block erase ERES operation may not be finished. Model No.: LRS1383 March 1, 2001 37 (at the same PPH1/2 and WP# must also IH ...
Page 84
... FUM00701 Figure 9. Block Erase Suspend and Block Erase Resume Flowchart Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Bus Command Operation Block Erase Data=B0H Write Suspend Addr=Within Partition Read Status Data=70H Write Register Addr=Within Partition Status Register Data Read Addr=Within Partition Check SR.7 Standby 1=WSM Ready 0=WSM Busy Check SR ...
Page 85
... Buffer) Program Resume command, the Block Erase Resume command is ignored and the partition to which the Block Erase Resume command is written is set to read array mode with block erase suspended defines the EHRH1 Set Read and IH (at the same level IH Model No.: LRS1383 Rev. 2.20 March 1, 2001 39 ...
Page 86
... Program Suspend Read Status Write Register Read Standby Standby Write Read (Page Buffer) Write Program Resume Model No.: LRS1383 March 1, 2001 40 Comments Data=B0H Addr=Within Partition Data=70H Addr=Within Partition Status Register Data Addr=Within Partition Check SR.7 1=WSM Ready 0=WSM Busy Check SR.2 1=(Page Buffer) Program ...
Page 87
... Locked 1 0 Lock-down Disable 1 1 Lock-down Disable =0: a block is unlocked. 0 =0: a block is not locked-down [110] state, the state changes to [011] and the blocks are IL Model No.: LRS1383 . If the output (1) and Block Lock-Down Erase/Program Allowed? Yes No No Yes No Yes No ...
Page 88
... WP# is driven [110] state, the state changes to [011] and the blocks are Model No.: LRS1383 March 1, 2001 42 (4) (1) (1) Set Lock-down (2) [011] [011] No Change (2) [111] [111] (2) [111] No Change =0), the ...
Page 89
... Write FFH after a sequence of set block lock/lock-down bit operations to place device in read array mode. Bus Command Operation Read Status Data=70H Write Register Addr=Within Partition Status Register Data Read Addr=Within Partition Check SR.7 Standby 1=WSM Ready 0=WSM Busy Model No.: LRS1383 March 1, 2001 43 Comments (see Table 6 through / Comments Rev. 2.20 ...
Page 90
... Subsequent reads at Block Base Address +2 (see Table 6 through Table 8) will output the lock/unlock status of that block. The lock-down status is represented by the output pin the output bit is set correctly. Figure 11 shows set block lock-down bit flowchart. Model No.: LRS1383 March 1, 2001 blocks that were IL is " ...
Page 91
... FUM00701 Figure 12. Clear Block Lock Bit Flowchart Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Bus Command Operation <First cycle> Data=60H Addr=Within Block to be Unlocked Clear Block Write Lock Bit <Second cycle> Data= D0H Addr=Within Block to be Unlocked Status Register Data Read Addr=Within Partition Check SR ...
Page 92
... To return to the read array mode, write the Read Array command (FFH) to the partition’s CUI after the completion of the OTP program operation. Model No.: LRS1383 March 1, 2001 the absence of this ...
Page 93
... FUM00701 Figure 13.1. Automated OTP Program Flowchart Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Bus Command Operation <First cycle> Data=C0H Write Addr=Location to be Programmed OTP Program <Second cycle> Data=Data to be Write Programmed Addr=Location to be Programmed Status Register Data Read Addr=X Check SR.7 Standby 1=WSM Ready 0=WSM Busy Repeat for subsequent OTP program ...
Page 94
... FUM00701 Figure 13.2. Automated OTP Program Flowchart (Continued) Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 Bus Command Operation Check SR.3 Standby 1=V Error Detect PP Check SR.1 Standby 1=Device Protect Detect Check SR.4 Standby 1=OTP Program Error SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are programmed before full status is checked ...
Page 95
... Status register, query code, identifier codes, OTP block and configuration register codes can only be read in single asynchronous or single synchronous read mode. Figure 14. Frequency Configuration Model No.: LRS1383 - A contains the read 15 0 (Read Mode) Rev ...
Page 96
... RCR.3. In the asynchronous page mode, the burst length always equals 8 words. All the bits in the read configuration register are set to "1" after power-up or device reset. When the bit RCR.15 is set to "1", other bits are invalid. Model No.: LRS1383 R DOC ...
Page 97
... Table 14), determines the number of clocks that data will be held valid. The data hold time for the LH28F320BX/ ) LH28F640BX series can be set to one clock or two clocks IL (see Figure 15). for different IL Figure 15. Output Configuration Model No.: LRS1383 TBD ns TBD MHz TBD MHz TBD MHz TBD MHz Rev. 2.20 March 1, 2001 51 ...
Page 98
... If the burst read never crosses a 64-word boundary, the delay will never happen. The WAIT# output pin is used in continuous burst mode or 4-, 8-word burst with no-wrap mode to inform the system if this output delay occurs. Model No.: LRS1383 March 1, 2001 52 Rev. 2.20 ...
Page 99
... Table 16. Read Sequence and Burst Length Burst Addressing Sequence [Decimal] 8-Word Burst Length (RCR.2-0=010) Intel Linear 0-1-2-3 0-1-2-3-4-5-6-7 1-0-3-2 1-2-3-4-5-6-7-0 2-3-0-1 2-3-4-5-6-7-0-1 3-2-1-0 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 NA 0-1-2-3-4-5-6-7 NA 1-2-3-4-5-6-7-8 NA 2-3-4-5-6-7-8-9 NA 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12- 13 7-8-9-10-11-12-13- 14 Model No.: LRS1383 Cotinuous Burst (RCR.2-0=111) Intel Linear 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6… 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7… 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8… 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9… 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10… 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11… 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12… 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13… 14-15-16-17-18-19-20… 15-16-17-18-19-20-21… NA 0-1-2-3-4-5-6… NA 1-2-3-4-5-6-7… NA 2-3-4-5-6-7-8… NA 3-4-5-6-7-8-9… NA 4-5-6-7-8-9-10… ...
Page 100
... After a successful set read/partition configuration register operation, the device returns to read array mode. Bus Command Operation Read Status Write Register Read Standby Model No.: LRS1383 March 1, 2001 54 Comments <First cycle> Data=60H Addr=Configuration Register Code (see Table 14 or Table 17) <Second cycle> Data= 03H (Read ...
Page 101
... There are three partitions in this configuration. Plane1-2 are merged to one partition. If the partition configuration register bits are set to "111", there are four partitions. Each partition is just the same as each plane. Figure 17 illustrates the various partition configuration. PP Model No.: LRS1383 March 1, 2001 55 Rev. 2.20 ...
Page 102
... See Figure 17 for the detail on partition configuration. 3. PCR.15-11 and PCR.7-0 bits are reserved for future use. If these bits are read via the Read Identifier Codes/OTP command, the device may output "1" or "0" on these bits. Figure 17. Partition Configuration Model No.: LRS1383 PC2 PC1 10 9 ...
Page 103
... Write the proper command again after V and GND. CC transitions above V Model No.: LRS1383 Traces on Printed Circuit Boards PP pin on the LH28F320BX/LH28F640BX series PP supplies the currents on the printed ...
Page 104
... Machine) and sets the status register to 80H. After return from reset, a time t outputs are valid, and a delay regardless required before a write sequence can be initiated. After IH this wake-up interval, normal operation is restored. Model No.: LRS1383 current is comparable provide new data when addresses are AVQV to protect data against IL ...
Page 105
... OTP block. • For detailed description on RST# control, refer to Section 5.1.5. Protection against noises on WE# signal To prevent the recognition of false commands as write commands, system designer should consider the method for reducing noises on WE# signal. Model No.: LRS1383 March 1, 2001 59 control PP is lower than V (V ...
Page 106
... IH mode read timing with ADV# held low. Note that the address A must be toggled to output the page-mode 2-0 data. In asynchronous read mode, the output of WAIT# is fixed Model No.: LRS1383 March 1, 2001 60 , the latch is open. The latch IL . This stores asynchronous mode Holding CLK and ADV# ...
Page 107
... Addresses are lathed when ADV# is driven high or upon the rising or falling edge of CLK while ADV word, 8-word or continuous burst accesses is not available in this mode. Therefore, the external input addresses must be incremented every read cycle. Model No.: LRS1383 March 1, 2001 61 , the WAIT# output buffer IH ...
Page 108
... FUM00701 Figure 18. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks (A is not used for 32M-bit device.) 21 Synchronous burst mode will be available for future device. Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001 62 Rev. 2.20 ...
Page 109
... Figure 19. AC Waveform for Synchronous Burst Mode Read Operations from Main Blocks or Parameter Blocks in 4-Word Burst Mode: RCR.2-0=001 (A is not used for 32M-bit device.) 21 Synchronous burst mode will be available for future device. Synchronous burst mode will be available for future device. Appendix to Spec No.: MFM2-J13207 FUM00701 Model No.: LRS1383 March 1, 2001 63 Rev. 2.20 ...
Page 110
... FUM00701 Figure 20. AC Waveform for an Output Delay when Continuous Burst Read with Data Output Configurations Set to One Clock (A is not used for 32M-bit device.) 21 Synchronous burst mode will be available for future device. Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001 64 Rev. 2.20 ...
Page 111
... Figure 21. AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code (A is not used for 32M-bit device.) 21 Synchronous burst mode will be available for future device. Appendix to Spec No.: MFM2-J13207 FUM00701 Model No.: LRS1383 March 1, 2001 65 Rev. 2.20 ...
Page 112
... Figure 22. AC Waveform for Single Synchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code (A is not used for 32M-bit device.) 21 Synchronous burst mode will be available for future device. Appendix to Spec No.: MFM2-J13207 FUM00701 Model No.: LRS1383 March 1, 2001 66 Rev. 2.20 ...
Page 113
... Common Flash Interface or CFI. Common Flash Interface for LH28F640BX series is now under development. Query code is described in the next version of Appendix. Appendix to Spec No.: MFM2-J13207 FUM00701 the LH28F320BX/ Model No.: LRS1383 Rev. 2.20 March 1, 2001 67 ...
Page 114
... AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. Appendix to Spec No.: MFM2-J13207 FUM00701 (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP Model No.: LRS1383 Rev. 2.20 March 1, 2001 68 ...