lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 101

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

4.17 Set Partition Configuration Register
The Partition Configuration Register (PCR) bits are set by
writing the Set Partition Configuration Register command
to the device.
This operation is initiated by a two-cycle command
sequence. The partition configuration register can be
configured by writing the command with the partition
configuration register code. At the first cycle, command
(60H) and a partition configuration register code is
written. At the second cycle, command (04H) and the
same address as the first cycle is written. The partition
configuration register code is placed on the address bus,
A
or WE# (whichever occurs first). The partition
configuration register code sets the partition boundaries.
This command functions independently of the V
voltage. RST# must be at V
command, the device returns to read array mode and
status registers are cleared. Figure 16 shows set partition
configuration register flowchart.
NOTES:
15
• The partition configuration register code can be read
• Partition configuration after device power-up or reset
via the Read Identifier Codes/OTP command (90H).
Address 0006H on A
configuration register code (see Table 6 through Table
8).
is as follows.
(Partition configuration register bits are volatile.)
- A
Plane 0-2 are merged into one partition.
Plane1-3 are merged into one partition.
Command
0
, and is latched on the rising edge of ADV#, CE#,
(top parameter device)
(bottom parameter device)
15
- A
Appendix to Spec No.: MFM2-J13207
0
IH
contains the partition
. After executing this
FUM00701
PP
Model No.: LRS1383
4.17.1 Partition Configuration
The partition configuration shown in Table 17 determines
the partiton boundaries for the dual work (simultaneous
read while erase/program) operation. The partition
boundaries can be set to any plane boundaries. If the
partition configuration register bits PCR.10-8 (PC.2-0)
are set to "001", the partition boundary is set between
plane0 and plane1. There are two partitions in this
configuration. Plane1-3 are merged to one partition.
Status registers for plane1-3 are also merged to one. If the
partition configuration register bits are set to "101", the
partition boundaries are set between plane0 and plane1
and between plane2 and plane3. There are three partitions
in this configuration. Plane1-2 are merged to one
partition. If the partition configuration register bits are set
to "111", there are four partitions. Each partition is just
the same as each plane. Figure 17 illustrates the various
partition configuration.
March 1, 2001
Rev. 2.20
55