lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 7
lrs1383
Manufacturer Part Number
lrs1383
Description
Stacked Chip 32m Flash And 8m Sram
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LRS1383.pdf
(114 pages)
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3. Truth Table
3.1 Bus operation
Notes:
Read
Output
Disable
Write
Standby
Reset Power
Down
Standby
Reset Power
Down
1. L = V
2. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed
3. Never hold F-OE low and F-WE low at the same timing.
4. Refer Section 5. Command Definitions for Flash Memory valid D
5. F-WP set to V
6. Electricity consumption is lowest when F-RST = GND ±0.2V.
7. Flash Read Mode
8. SRAM Standby Mode
Read Array
Read Identifier Codes/OTP
Read Query
S-CE
Flash
H
X
X
when F-V
Block erase, full chip erase, (page buffer) program or OTP program with F-V
results and should not be attempted.
1
S-CE
IL
, H = V
X
X
L
Standby
Read
Output
Disable
Write
Read
Output
Disable
Write
Standby
SRAM
PP
2
Mode
= V
(1)
IL
S-LB
IH
X
X
H
or V
PPH1/2
, X = H or L. High-Z = High impedance. Refer to the DC Characteristics.
2,3,4,5
Notes
3,5
5,6
5,6
5,6
5,6
IH
5
5
5
5
5
S-UB
.
and F-V
X
X
H
F-CE
H
X
H
X
L
CC
= 2.7V to 3.3V.
Refer to the Appendix
F-RST F-OE F-WE S-CE
H
H
H
L
L
See 5.2, 5.3
Address
9. S-UB, S-LB Control Mode
S-LB
X
H
X
X
X
L
H
L
L
L R S1 3 8 3
S-UB
H
X
X
X
L
H
L
L
DQ
L
L
D
D
High-Z
OUT
OUT
IN
1
(8)
(8)
Refer to the Appendix
0
to DQ
S-CE
during a write operation.
/D
/D
H
H
DQ
See 5.2, 5.3
IN
IN
2
7
0
D
to DQ
OUT
S-OE S-WE S-LB S-UB DQ
DQ
X
H
X
X
H
X
X
X
L
L
D
D
High-Z
OUT
OUT
8
15
PP
to DQ
/D
/D
X
H
X
H
X
< V
H
L
H
L
X
IN
IN
15
PPH1/2
X
H
X
H
(8)
(8)
(Min.) produce spurious
X
H
X
H
(9)
(9)
(9)
(9)
High-Z
High-Z
High-Z
High-Z
0
D
to DQ
(7)
IN
15
5
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