lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 88

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

Other than [110]
NOTES:
1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit
2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ
3. "No Change" means that the state remains unchanged after the command written.
4. In this state transitions table, assumes that WP# is not changed and fixed V
Previous State
NOTES:
1. "WP#=0 1" means that WP# is driven to V
2. State transition from the current state [011] to the next state depends on the previous state.
3. When WP# is driven to V
4. In this state transitions table, assumes that lock configuration commands are not written in
[000]
[001]
[100]
[101]
[011]
[110]
[111]
State
command and "Set Lock-down" means Set Block Lock-Down Bit command.
corresponding block is locked-down and automatically locked at the same time.
V
automatically locked.
previous, current and next state.
[110]
IL
-
-
-
-
-
-
(2)
Current State
WP#
0
0
0
1
1
1
1
(2)
Table 13. Block Locking State Transitions upon WP# Transition
Appendix to Spec No.: MFM2-J13207
Table 12. Block Locking State Transitions upon Command Write
DQ
1
0
0
1
0
0
1
[000]
[001]
[011]
[100]
[101]
[110]
[111]
State
1
DQ
0
1
1
0
1
0
1
0
Current State
IL
WP#
0
0
0
1
1
1
1
in [110] state, the state changes to [011] and the blocks are
No Change
Set Lock
No Change
No Change
No Change
FUM00701
[001]
[101]
Result after Lock Command Written (Next State)
[111]
DQ
0
0
1
0
0
1
1
1
(1)
(3)
Model No.: LRS1383
IH
DQ
0
1
1
0
1
0
1
and "WP#=1 0" means that WP# is driven to
0
Result after WP# Transition (Next State)
Clear Lock
WP#=0 1
No Change
No Change
No Change
No Change
[000]
[100]
[110]
[100]
[101]
[110]
[111]
-
-
-
-
March 1, 2001
(1)
(1)
IL
Set Lock-down
(4)
or V
(4)
WP#=1 0
No Change
No Change
[011]
[111]
[111]
IH
[011]
[000]
[001]
[011]
[011]
[111]
.
-
-
-
-
(2)
(2)
(2)
0
(3)
=0), the
(1)
(1)
Rev. 2.20
42