lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 96

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

RCR.15 = READ MODE (RM)
RCR.14 = RESERVED FOR FUTURE ENHANCEMENTS
RCR.13-11 = FREQUENCY CONFIGURATION (FC2-0)
RCR.10 = RESERVED FOR FUTURE ENHANCEMENTS
RCR.9 = DATA OUTPUT CONFIGURATION (DOC)
RCR.8 = WAIT# CONFIGURATION (WC)
RCR.7 = BURST SEQUENCE (BS)
RCR.6 = CLOCK CONFIGURATION (CC)
RCR.5-4 = RESERVED FOR FUTURE ENHANCEMENTS
RCR.3 = BURST WRAP (BW)
RCR.2-0 = BURST LENGTH (BL2-0)
• 0 = Synchronous Burst Reads Enabled
• 1 = Asynchronous Reads Enabled (Default)
• 000 = Code 0 reserved for future use
• 001 = Code 1 reserved for future use
• 010 = Code 2
• 011 = Code 3
• 100 = Code 4
• 101 = Code 5
• 110 = Code 6 reserved for future use
• 111 = Code 7 reserved for future use (Default)
• 0 = Hold Data for One Clock
• 1 = Hold Data for Two Clocks (Default)
• 0 = WAIT# Asserted During Delay
• 1 = WAIT# Asserted One Data Cycle Before Delay
• 0 = Intel Burst Order
• 1 = Linear Burst Order (Default)
• 0 = Burst Starts and Data Output on Falling Clock Edge
• 1 = Burst Starts and Data Output on Rising Clock Edge
• 0 = Wrap Burst Reads within Burst Length set
• 1 = No Wrap Burst Reads within Burst Length set
• 001 = 4 Word Burst
• 010 = 8 Word Burst
• 011 = Reserved for future use
• 111 = Continuous (Linear) Burst (Default)
(Default)
(Default)
by RCR.2-0
by RCR.2-0 (Default).
RM
BS
15
7
(R)
(R)
(R)
CC
14
R
6
Synchronous burst mode will be available for future device.
Appendix to Spec No.: MFM2-J13207
FC2
Table 14. Read Configuration Register Definition
13
R
5
FC1
12
R
4
FUM00701
Model No.: LRS1383
Read configuration register affects the read operations from
main and parameter blocks. Read operations for status
register, query code, identifier codes, OTP block and device
configuration codes support single read cycles.
RCR.14, RCR.10, RCR.5 and RCR.4 bits are reserved for
future use.
Refer to Frequency Configuration in Section 4.16.2 for
information about the frequency configuration RCR.13-11.
Undocumented combinations of bits RCR.13-11 are reserved
by Sharp Corporation for future implementations and should
not be used.
Refer to Section 4.16.7 for information about Burst Wrap
configuration RCR.3.
In the asynchronous page mode, the burst length always
equals 8 words.
All the bits in the read configuration register are set to "1"
after power-up or device reset.
When the bit RCR.15 is set to "1", other bits are invalid.
FC0
BW
11
3
March 1, 2001
BL2
10
R
2
NOTES:
DOC
BL1
9
1
Rev. 2.20
BL0
WC
8
0
50