lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 47

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

1 Introduction.............................................................. 2
2 Principles of Operation .......................................... 14
3 Bus Operation ........................................................ 15
4 Command Definitions ............................................ 18
1.1 Features ............................................................. 2
1.2 Definition of Block, Plane and Partition........... 2
1.3 Product Overview ............................................. 2
1.4 Product Description........................................... 8
2.1 Operation Mode after Power-up
2.2 Read, Program and Erase Operation ............... 14
2.3 Status Register for Each Partition ................... 14
2.4 Data Protection................................................ 14
3.1 Read Array ...................................................... 15
3.2 Output Disable ................................................ 15
3.3 Standby............................................................ 15
3.4 Reset................................................................ 15
3.5 Read Identifier Codes/OTP............................. 16
3.6 Read Query ..................................................... 16
3.7 Write the Command to the CUI ...................... 16
4.1 Read Array Command .................................... 18
4.2 Read Identifier Codes/OTP Command ........... 18
4.3 Read Query Command.................................... 23
4.4 Read Status Register Command...................... 23
4.5 Clear Status Register Command ..................... 23
4.6 Block Erase Command.................................... 26
4.7 Full Chip Erase Command.............................. 26
4.8 Program Command ......................................... 31
4.9 Page Buffer Program Command ..................... 31
4.10 Block Erase Suspend Command
4.11 (Page Buffer) Program Suspend
4.12 Set Block Lock Bit Command ...................... 41
1.4.1 Memory Block Organization ..................... 8
1.4.2 Four Physical Planes .................................. 8
1.4.3 Partition ...................................................... 8
1.4.4 Parameter Block ......................................... 8
1.4.5 Main Block................................................. 8
1.4.6 OTP (One Time Program) block................ 8
or Reset Mode ............................................. 14
and Block Erase Resume Command ........... 37
Command and (Page Buffer) Program
Resume Command ...................................... 39
Synchronous burst mode will be available for future device.
Appendix to Spec No.: MFM2-J13207
PAGE
CONTENTS
FUM00701
Model No.: LRS1383
5 Design Considerations ........................................... 57
6 Common Flash Interface........................................ 67
7 Related Document Information.............................. 68
4.13 Clear Block Lock Bit Command................... 44
4.14 Set Block Lock-Down Bit Command ........... 44
4.15 OTP Program Command............................... 46
4.16 Set Read Configuration Register
4.17 Set Partition Configuration Register
5.1 Hardware Design Considerations.................... 57
5.2 Software Design Considerations..................... 59
5.3 Data Protection Method .................................. 59
5.4 High Performance Read Mode........................ 60
4.16.1 Device Read Configuration.................... 49
4.16.2 Frequency Configuration ....................... 51
4.16.3 Data Output Configuration..................... 51
4.16.4 WAIT# Configuration............................ 52
4.16.5 Burst Sequence....................................... 52
4.16.6 Clock Configuration............................... 52
4.16.7 Burst Wrap ............................................. 52
4.16.8 Burst Length........................................... 52
4.17.1 Partition Configuration .......................... 55
5.1.1 Control using RST#, CE# and OE# ......... 57
5.1.2 Power Supply Decoupling ....................... 57
5.1.3 VPP Traces on Printed Circuit Boards..... 57
5.1.4 VCC, VPP, RST# Transitions.................. 57
5.1.5 Power-Up/Down Protection..................... 58
5.1.6 Power Dissipation .................................... 58
5.1.7 Automatic Power Savings........................ 58
5.1.8 Reset Operation........................................ 58
5.2.1 WSM (Write State Machine) Polling....... 59
5.2.2 Attention to Program Operation............... 59
5.4.1 CPU Compatibility................................... 60
5.4.2 Features of ADV# and CLK .................... 60
5.4.3 Address Latch .......................................... 60
5.4.4 Using Asynchronous Page Mode............. 60
5.4.5 Using Synchronous Burst Mode .............. 61
5.4.6 Using WAIT# in Burst Mode................... 61
5.4.7 Single Read Mode.................................... 61
4.16.8.1 Continuous Burst Length ................ 52
Command .................................................... 49
Command .................................................... 55
March 1, 2001
Rev. 2.20
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