lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 63

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

Applying the specified voltage on V
V
buffer) program or OTP program with writing the proper
command and address to the CUI. Erase or program
operation may occur in only one partition at a time. Other
partitions must be in one of the read modes.
The Block Erase
command and an address within the block to be erased.
The Full Chip Erase command requires appropriate
command. The (Page Buffer) Program command requires
appropriate command and an address of the location to be
programmed. The Set/Clear Block Lock Bit or Set Block
Lock-down Bit command requires appropriate command
and an address within the target block. The OTP Program
command requires appropriate command and an address
of the location to be programmed within the OTP block.
The Set Read Configuration Register command or the Set
Partition Configuration Register command requires
appropriate command and configuration register code
presented on the addresses A
The CUI itself does not occupy an addressable memory
location. When both CE# and WE# go V
command is written to CUI and the address and data are
latched on the rising edge of CE# or WE#, whichever
goes high first. The command can be written to the CUI at
the standard microprocessor writing timing.
PP
enables successful block erase, full chip erase, (page
command
0
Appendix to Spec No.: MFM2-J13207
-A
15
.
requires appropriate
CC
and V
IL
(valid), the
PPH1/2
FUM00701
on
Model No.: LRS1383
March 1, 2001
Rev. 2.20
17