lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 87

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

4.12 Set Block Lock Bit Command
The LH28F320BX/LH28F640BX series is provided with
a block lock bit for each parameter block and main block.
The features of set block lock bit is as follows:
The Set Block Lock Bit command is a two-cycle
command. At the first cycle, command (60H) and an
address within the block to be locked is written to the
target partition. At the second cycle, command (01H) and
the same address as the first cycle is written. Read
operations to the target partition output the status register
• Any block can be independently locked by setting its
• The time required for block locking is less than the
• Block erase, full chip erase or (page buffer) program
• At power-up or device reset, all blocks default to
block lock bit.
minimum command cycle time (minimum time from
the rising edge of CE# or WE# to write the command
to the next rising edge of CE# or WE#).
on a locked block cannot be executed (see Table 11
and Table 12).
locked state, regardless of the states before power-off
or reset operation.
(Lock bit is volatile.)
NOTES:
1. OTP (One Time Program) block has the lock function which is different from those described
2. DQ
3. Erase and program are general terms, respectively, to express: block erase, full chip erase and
4. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,
5. When WP# is driven to V
above.
(page buffer) program operations.
[001] (WP#=0) or [101] (WP#=1), regardless of the states before power-off or reset operation.
automatically locked.
DQ
[000]
[001]
[011]
[100]
[101]
[110]
[111]
State
0
1
=1: a block is locked; DQ
=1: a block is locked-down; DQ
(5)
(4)
(4)
Appendix to Spec No.: MFM2-J13207
WP#
0
0
0
1
1
1
1
Table 11. Functions of Block Lock
DQ
0
0
1
0
0
1
1
1
(2)
Current State
IL
0
=0: a block is unlocked.
in [110] state, the state changes to [011] and the blocks are
DQ
0
1
1
0
1
0
1
0
(2)
1
FUM00701
=0: a block is not locked-down.
Unlocked
Locked
Locked-down
Unlocked
Locked
Lock-down Disable
Lock-down Disable
Model No.: LRS1383
data until another valid command is written. After writing
the second cycle command, the block lock bit is set within
the minimum command cycle time and the corresponding
block is locked. To check the lock status, write the Read
Identifier Codes/OTP command (90H) and an address
within the target block. Subsequent reads at Block Base
Address +2 (see Table 6 through Table 8) will output the
lock/unlock status of that block. The lock/unlock status is
represented by the output pin DQ
"1", the block lock bit is set correctly. Figure 11 shows set
block lock bit flowchart.
The two-cycle command sequence ensures that block is
not accidentally locked. An invalid Set Block Lock Bit
command sequence will result in both status register bits
SR.5 and SR.4 being set to "1" and the operation will not
be executed.
The Set Block Lock Bit command is available when the
power supply voltage is specified level, independent of
the voltage on V
At power-up or device reset, since all blocks default to
locked state, write the Clear Block Lock Bit command
described later to clear block lock bit before a erase or
program operation.
State Name
(1)
and Block Lock-Down
March 1, 2001
PP
.
Erase/Program Allowed?
0
. If the output of DQ
Yes
Yes
Yes
No
No
No
No
Rev. 2.20
(3)
41
0
is