lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 97

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

4.16.2 Frequency Configuration
The read configuration register bits RCR.13, RCR.12 and
RCR.11 indicates the frequency configuration (see Table
14). The frequency configuration informs the number of
clocks that must elapse after ADV# is driven active (V
before data will be available. This value is determined by
the input clock frequency. See Table 15 for the specific
input CLK frequency configuration. Figure 14 shows data
output latency from ADV# going V
frequency configuration codes.
RCR.13 RCR.12 RCR.11
Read Configuration Register
0
0
1
1
1
1
0
0
Synchronous burst mode will be available for future device.
Table 15. Frequency Configuration Settings
0
1
0
1
Appendix to Spec No.: MFM2-J13207
Configuration Code
Frequency
IL
2
3
4
5
for different
Figure 15. Output Configuration
FUM00701
IL
)
TBD MHz
TBD ns
24MHz
36MHz
40MHz
Model No.: LRS1383
Input Clock Frequency
4.16.3 Data Output Configuration
The data output configuration, shown by RCR.9 (see
Table 14), determines the number of clocks that data will
be held valid. The data hold time for the LH28F320BX/
LH28F640BX series can be set to one clock or two clocks
(see Figure 15).
TBD MHz
TBD MHz
TBD MHz
TBD MHz
TBD ns
March 1, 2001
Rev. 2.20
51