lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 70

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

SR.7 = WRITE STATE MACHINE STATUS (WSMS)
SR.15 - SR.8 = RESERVED FOR FUTURE
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
SR.5 = BLOCK ERASE AND FULL CHIP ERASE
SR.4 = (PAGE BUFFER) PROGRAM AND
SR.3 = V
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
• 1 = Ready
• 0 = Busy
• 1 = Block Erase Suspended
• 0 = Block Erase in Progress/Completed
• 1 = Error in Block Erase or Full Chip Erase
• 0 = Successful Block Erase or Full Chip Erase
• 1 = Error in (Page Buffer) Program or OTP Program
• 0 = Successful (Page Buffer) Program or OTP Program
• 1 = V
• 0 = V
• 1 = (Page Buffer) Program Suspended
• 0 = (Page Buffer) Program in Progress/Completed
• 1 = Erase or Program Attempted on a
• 0 = Unlocked
ENHANCEMENTS (R)
Locked Block, Operation Abort
WSMS
15
R
7
PP
PP
STATUS (BEFCES)
STATUS (PBPSS)
OTP PROGRAM STATUS (PBPOPS)
PP
LOW Detect, Operation Abort
OK
STATUS (VPPS)
BESS
14
R
6
Appendix to Spec No.: MFM2-J13207
BEFCES
13
R
5
Table 9. Status Register Definition
PBPOPS
12
R
4
FUM00701
Model No.: LRS1383
Status Register indicates the status of the partition, not WSM
(Write State Machine). Even if the SR.7 is "1", the WSM may
be occupied by the other partition when the device is set to 2,
3 or 4 partitions configuration.
Check SR.7 to determine block erase, full chip erase, (page
buffer) program or OTP program completion. SR.6 - SR.0 are
invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, page buffer program, set/clear block lock bit, set block
lock-down bit or set read/partition configuration register
attempt, an improper command sequence was entered.
SR.3 does not provide a continuous indication of V
The WSM interrogates and indicates the V
Block Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. SR.3 is not guaranteed to
report accurate feedback when V
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. It informs the system,
depending on the attempted operation, if the block lock bit is
set. Reading the block lock configuration codes after writing
the Read Identifier Codes/OTP command indicates block
lock bit status.
SR.15 - SR.8 and SR.0 are reserved for future use and should
be masked out when polling the status register.
VPPS
11
R
3
PBPSS
March 1, 2001
10
R
2
NOTES:
PP
DPS
V
R
9
1
PPH1
, V
PP
level only after
PPH2
Rev. 2.20
or V
PP
R
R
8
0
24
level.
PPLK
.