lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 104

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

5.1.5 Power-Up/Down Protection
The LH28F320BX/LH28F640BX series is designed to
offer protection against accidental block erase, full chip
erase, (page buffer) program, OTP program due to noises
during power transitions. When the device power-up,
holding V
specified level and in stable. For additional information,
please refer to the AP-007-SW-E RST#, V
Potential Switching Circuit. After power-up, the
LH28F320BX/LH28F640BX series defaults to the mode
described in Section 2.1.
System designers must guard against spurious writes
when V
above V
following design considerations. Since both CE# and
WE# must be at V
signal to V
architecture provides additional protection because
alternation of memory contents can only occur after
successful completion of the two-step command
sequences.
The individual block locking scheme, which enables each
block to be independently locked, unlocked or locked-
down, prevents the accidental data alternation. The device
is also disabled until RST# is brought to V
of the state of its control inputs. By holding the device in
reset during power-up/down, invalid bus conditions can
be masked, providing yet another level of memory
protection.
5.1.6 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during system
idle time. The LH28F320BX/LH28F640BX series’
nonvolatility increases usable battery life because data is
retained when system power is removed.
CC
PPLK
PP
voltages are above V
IH
and RST# to GND until V
, by referring to Section 5.3 and the
will inhibit writes to the device. The CUI
IL
for a command write, driving either
Appendix to Spec No.: MFM2-J13207
LKO
and V
CC
has reached the
PP
IH
voltages are
PP
, regardless
Electric
FUM00701
Model No.: LRS1383
5.1.7 Automatic Power Savings
Automatic Power Savings (APS) provides low-power
operation during active mode. APS mode allows the flash
memory to put itself into a low current state when not
being accessed. After data is read from the memory array
and addresses not switching, the device enters the APS
mode where typical I
The flash memory stays in this static state with outputs
valid until a new location is read. Standard address access
timings (t
changed. During dual work operation (one partition being
erased or programmed, while other partitions are one of
read modes), the device cannot enter the APS mode even
if the input address remains unchanged.
5.1.8 Reset Operation
During power-up/down or transitions of power supply
voltage, hold the RST# pin at V
noises which are caused by invalid bus conditions and
initialize the internal circuitry in flash memory. Bringing
RST# to V
Machine) and sets the status register to 80H.
After return from reset, a time t
outputs are valid, and a delay, t
required before a write sequence can be initiated. After
this wake-up interval, normal operation is restored.
AVQV
IL
) provide new data when addresses are
resets the internal WSM (Write State
March 1, 2001
CC
current is comparable to I
IL
PHQV
to protect data against
PHWL
is required until
and t
Rev. 2.20
PHEL
58
CCS
, is
.