lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 83

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

4.10 Block Erase Suspend Command and
The Block Erase Suspend command (B0H) allows block
erase interruption to read or program data in the blocks
other than that which is suspended. This command is
valid for the block erase operation and the full chip erase
operation can not be suspended.
Once the block erase process starts in a partition, writing
the Block Erase Suspend command to the partition
requests that the WSM suspends the block erase sequence
at a predetermined point in the algorithm. Read
operations to the target partition after writing the Block
Erase Suspend command access the status register. Status
register bits SR.7 and SR.6 indicate if the block erase
operation has been suspended (both will be set to "1").
Specification t
suspend latency.
When the Block Erase Suspend command is written after
the completion of the block erase operation, the partition
returns to read array mode. Therefore, the Read Status
Register command (70H) must be written to the target
partition after writing the Block Erase Suspend command.
If the status register bits SR.7 and SR.6 are set to "1",
block erase has been suspended.
At this point, a Read Array command can be written to
read data from blocks other than that which is suspended.
A (Page Buffer) Program command sequence can also be
written during block erase suspend to program data in
other blocks. Using the (Page Buffer) Program Suspend
command (see Section 4.11), a program operation can
also be suspended during a block erase suspend.
During a word program operation with block erase
suspended, status register bit SR.7 will return to "0".
However, SR.6 will remain "1" to indicate the block erase
suspend status.
If the Page Buffer Program setup command (E8H) is
written to the target partition during block erase suspend
in which SR.7 and SR.6 are set to "1", read operations to
the target partition to be programmed output the extended
status register data. In read extended status register mode,
bit XSR.7 is only valid, which indicates that the written
command (E8H) is available, and other bits (from XSR.6
to XSR.0) are invalid (see Table 10). When writing the
word count [N]-1 and start address at next command
cycle, the target partition returns to read status register
mode and the status register bits SR.7 and SR.6 are set to
"1". After the Page Buffer Program confirm command
(D0H) is written, the status register bit SR.7 will return to
Block Erase Resume Command
WHRH2
or t
EHRH2
Appendix to Spec No.: MFM2-J13207
defines the block erase
FUM00701
Model No.: LRS1383
"0". However, SR.6 will remain "1" to indicate the block
erase suspend status.
The only other valid commands while block erase is
suspended are Read Identifier Codes/OTP, Read Query,
Read Status Register, Set Block Lock Bit, Clear Block
Lock Bit, Set Block Lock-down Bit, Set Read
Configuration Register and Block Erase Resume
command.
To resume the block erase operation, write the Block
Erase Resume command (D0H) to the partition. Status
Register bits SR.7 and SR.6 will be automatically cleared.
After the Block Erase Resume command is written, the
target partition automatically outputs the status register
data when read. V
level before block erase suspended) while block erase is
suspended. RST# must remain at V
remain at V
suspended). Block erase cannot resume until (page
buffer) program operation initiated during block erase
suspend is completed. Figure 9 shows the block erase
suspend and block erase resume flowchart.
If the interval time from a Block Erase Resume command
to a subsequent Block Erase Suspend command is shorter
than t
operation may not be finished.
ERES
IL
and its sequence is repeated, the block erase
or V
March 1, 2001
PP
IH
must remain at V
(at the same level before block erase
IH
and WP# must also
PPH1/2
(at the same
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