gc41c501g0-sp8i CORERIVER Semiconductor, gc41c501g0-sp8i Datasheet - Page 14

• Manufacturer Part Number: gc41c501g0-sp8i
• Description: 4-bit Microcontrollers With Reduced 8051 Architecture With Reduced 8051 Architecture
• Manufacturer: CORERIVER Semiconductor

- : Unimplemented bit. Read as 0.
u: Remains unchanged.
x: The value of the bit is not determined.
Register
IAPCON
6.2. SFR Brief Description
CKCFG
IOCFG
LVCFG
REMC
DPH
GDH
SPH
GDL
DPL
SPL
P0
P4
P1
P2
P3
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Port 0 output register.
Port 4 output register.
The low nibble of data pointer (DPTR).
The high nibble of data pointer (DPTR).
Port 1 output register.
REM output control register.
The low nibble of stack pointer (SP).
The high nibble of stack pointer (SP).
Port 2 output register.
IAP (In Application Programming) Control register.
Can be accessed only if MAP1 is set and MAP0 is cleared.
The low nibble of general purpose data register
The high nibble of general purpose data register
Port 3 output register.
The clock configuration register. Initialized only by power-on-reset.
The I/O port configuration register. Initialized only by power-on-reset.
The LVD configuration register. Initialized only by power-on-reset.
Note for 8-pin devices.
- Not supported SFRs : P1, P3, P4, REMC.
- Writing to the not-supported SFRs may cause unexpected behavior.
Description
ATOM1.0 Family
Reset Value
Power-On
1111
1111
0000
1111
0000
1111
1111
0000
0000
0000
1111
0000
0000
1x00
--00
--01
Preliminary
Reset Value
Other
1111
1111
0000
1111
0000
1111
1111
0000
0000
0000
1111
uuuu
uu0u
uxuu
--00
--01
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