gc41c501g0-sp8i CORERIVER Semiconductor, gc41c501g0-sp8i Datasheet - Page 28
gc41c501g0-sp8i
Manufacturer Part Number
gc41c501g0-sp8i
Description
4-bit Microcontrollers With Reduced 8051 Architecture With Reduced 8051 Architecture
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC41C501G0-SP8I.pdf
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6.8. POR & LVD : Condition for power notch
Power-on-reset is independent of power-rising slope.
The cases of reset generation by VDD notch
Voltage
Voltage
VDD
When VDD fails for a short time, the duration of notch (T) has limitation like
above for the successful POR operation.
The duration (T) will be changed by the VDD value and the transition time
VDD=2V
Power slope = 0.25 V / 1 us
Power slope = 1.0 V / 1 us
T >10us
0V
T > 20us
0.5V
time
Yellow Region : Only RC-POR operates.
Blue Region
Green Region : Both POR's operate at the same time.
T > 40us
: Only LVD-POR operates.
1V
ATOM1.0 Family
Preliminary
time
[28]
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