gc41c501g0-sp8i CORERIVER Semiconductor, gc41c501g0-sp8i Datasheet - Page 29

• Manufacturer Part Number: gc41c501g0-sp8i
• Description: 4-bit Microcontrollers With Reduced 8051 Architecture With Reduced 8051 Architecture
• Manufacturer: CORERIVER Semiconductor

[Example of WDT Period]
6.9. WDT (Watchdog Timer)
WDT
WDT is reset by
XT/RG
1
0
0
Free running counter which resets CPU every 2
system clock cycles.
Although the counter length is fixed, WDT
overflow period may vary according to the current
frequency of system clock.
WDT is halt in STOP mode or disabled by user.
User S/W set WDTR bit in IFF[12]. WDTR bit is
automatically cleared by H/W after WDT is reset.
Internal reset caused by any source is activated.
Entering SLEEP mode.
Start of FLASH programming (erase/write) by IAP.
DIV2
0
0
1
DIV1
1
0
1
DIV0
1
0
0
F
OSC
3.64
7.28
7.28
(MHz)
F
F
OSC
17
F
OSC
F
OSC
SYS
/64
/8
Run Control of WDT
Program Sequence to disable WDT
WDT Period (ms)
MOV L, #11
SETB @L
MOV L, #13
CLR @L
MOV L, #11
CLR @L
1152
288
WDT may be disabled if WDTE flag in IFF[13] is
cleared.
When disabled WDT holds the state before.
User can modify WDTE if and only if MAP1 flag
in IFF[11] is set and MAP0 flag in IFF[10] is
cleared.
WDTE is set by internal reset and also set by
H/W when user sets SLEEP flag in IFF[14] or
writes IAPCON SFR.
18
; Enable MAP1
; Disable WDT
; Disable MAP1
ATOM1.0 Family
Preliminary
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