gc41c501g0-sp8i CORERIVER Semiconductor, gc41c501g0-sp8i Datasheet - Page 27
gc41c501g0-sp8i
Manufacturer Part Number
gc41c501g0-sp8i
Description
4-bit Microcontrollers With Reduced 8051 Architecture With Reduced 8051 Architecture
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC41C501G0-SP8I.pdf
(64 pages)
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LVD Pulse
6.8. POR & LVD : Power-On Reset
On-chip power-on reset is a logical OR of
RC-POR and LVD-POR
RC-POR operates when the rising time of
power (V
On-chip LVD
After POR pulse is off, the internal clock
stabilization counter starts to run, which
lengthens power-on reset about 4.5 ms.
3.3
1.7
1.6
0
Provides power-on reset when the rising time
of power is relatively long.
Power-on reset voltage is 1.7 V.
Provides power-fail reset when the power
goes down below 1.6 V.
Power-on Reset
DD
A
) is short.
1.7V
Power-fail Reset
1.6V
B
TIME
LVCFG (0Fh) : LVD Configuration Register
Reserved: Do not set these bits for the future compatibility.
POR
LVD_OFF
R/W(1)
POR
LVD-POR Block
STOP
LVD
: Power-on-reset flag to distinguish cold reset.
User need to mask out the reserved bits
by AND oprtation when referring to this bit.
Reserved
LVD Pulse
R(X)
RC-POR Block
ATOM1.0 Family
10 pF
1 MΩ
Reserved
R/W(0)
Preliminary
POR
Reserved
POR Reset
R/W(0)
[27]
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