gc41c501g0-sp8i CORERIVER Semiconductor, gc41c501g0-sp8i Datasheet - Page 52

• Manufacturer Part Number: gc41c501g0-sp8i
• Description: 4-bit Microcontrollers With Reduced 8051 Architecture With Reduced 8051 Architecture
• Manufacturer: CORERIVER Semiconductor

INC DPTR
Appendix A : Instruction Set (11/19)
Binary Code
Description
Carry Flag
Operation
Example
Cycles
Bytes
Increments the data pointer.
(DP) ← (DP) + 1
Not affected.
1
1
; Assumes all bits of DPTR is 1.
INC DPTR
INC DP
0000
0100
; By roll over, all bits
; This is also valid.
; of DPH and DPL are cleared.
JB bit, rel
Binary Code
L_BIT_SET:
Description
Carry Flag
Operation
Example
Cycles
Bytes
Branches if the bit in data memory is 1. The
address is given by DPTR and bit position is
given by two least significant bits of opcode .
The branch destination is computed by adding
the signed relative-displacement in the
second byte of the instruction to the PC, after
incrementing the PC to the start of the next
instruction. The contents of memory is not
affected.
(PC) ← (PC) + 2
IF M[DP].bit = 1 THEN (PC) ← (PC) + rel
Not affected.
2
2
JB 0, L_BIT_SET
......
......
1001
ATOM1.0 Family
11bb
; IF M[DP].0 = 0
; IF M[DP].0 = 1
rrrr
Preliminary
rrrr
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