gc41c501g0-sp8i CORERIVER Semiconductor, gc41c501g0-sp8i Datasheet - Page 53
gc41c501g0-sp8i
Manufacturer Part Number
gc41c501g0-sp8i
Description
4-bit Microcontrollers With Reduced 8051 Architecture With Reduced 8051 Architecture
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC41C501G0-SP8I.pdf
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JC rel
Appendix A : Instruction Set (12/19)
Binary Code
Description
Carry Flag
Operation
L_C_SET:
Example
Cycles
Bytes
Branches if the carry flag is 1.
The branch destination is computed by adding
the signed relative-displacement in the
second byte of the instruction to the PC, after
incrementing the PC to the start of the next
instruction.
(PC) ← (PC) + 2
IF (C) = 1 THEN (PC) ← (PC) + rel
Not affected.
2
2
JC L_C_SET
......
......
1001
0111
; IF (C) = 0
; IF (C) = 1
rrrr
rrrr
JMP addr
Binary Code
Description
Carry Flag
Operation
Example
Cycles
Bytes
Transfers program execution to the indicated
12-bit address.
The destination address is obtained by
concatenating the four low-order bits of the
opcode byte and the second byte of the
instruction.
(PC) ← addr
Not affected.
2
2
JMP LABEL ; Jumps to LABEL.
......
JMP .
1110
ATOM1.0 Family
aaaa
; Infinite loop
aaaa
Preliminary
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[53]
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