gc41c501g0-sp8i CORERIVER Semiconductor, gc41c501g0-sp8i Datasheet - Page 63

• Manufacturer Part Number: gc41c501g0-sp8i
• Description: 4-bit Microcontrollers With Reduced 8051 Architecture With Reduced 8051 Architecture
• Manufacturer: CORERIVER Semiconductor

IOCFG
LVCFG
Appendix B :
IOXEN
P2OEN
IOMAP [1:0] : Configure I/O ports mapping.
Reserved : Do not set these bits for the future compatibility.
POR
IOMAP1
R/W(0)
R/W(1)
POR
(0Eh) : I/O Port Configuration Register
(0Fh) : LVD Configuration Register
: Enable XI and XO as I/O ports.
: Configure P2 as push-pull output port.
: Power-on-reset flag.
0 : XI and XO are used for clock input (Default).
1 : XI and XO is used for PORT4[1:0]
User S/W may use this flag to distinguish cold reset
[0,0] : Default.
[0,1] : Optional 20-pin I/O port mapping
[1,0] : Optional 24-pin I/O port mapping
[1,1] : Reserved
and warm reset. User need to mask out the reserved bits
by AND oprtation when referring to this bit.
Reserved
IOMAP0
R/W(0)
R(X)
SFR Description [0Eh ~ 0Fh]
Reserved
R/W(0)
R/W(0)
P2OEN
Reserved
R/W(0)
R/W(0)
IOXEN
(3/3)
ATOM1.0 Family
Preliminary
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