SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 136

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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SuperI/O Module
Offset 02h
This register configures and controls the ACB functional block. It maintains the current ACB status and controls several ACB functions.
On reset and when the ACB is disabled, the non-reserved bits of ACBCST are cleared.
Offset 03h
7:6
Bit
1
0
5
4
3
2
1
0
7
6
5
4
3
Description
MASTER. (RO)
0: Arbitration loss (BER, bit 5, is set) or recognition of a Stop Condition.
1: Bus master request succeeded and master mode active.
XMIT (Transmit). (RO) Direction bit.
0: Master/slave transmit mode not active.
1: Master/slave transmit mode active.
Reserved.
TGABC (Toggle ABC Line). (R/W) Enables toggling the ABC line during error recovery.
0: Clock toggle completed.
1: When the ABD line is low, writing 1 to this bit toggles the ABC line for one cycle. Writing 1 to TGABC while ABD is high
TSDA (Test ABD Line). (RO) Reads the current value of the ABD line. It can be used while recovering from an error condi-
tion in which the ABD line is constantly pulled low by an out-of-sync slave. Data written to this bit is ignored.
GCMTCH (Global Call Match). (RO)
0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition).
1: In slave mode, ACBCTL1.GCMEN is set and the address byte (the first byte transferred after a Start Condition) is 00h.
MATCH (Address Match). (RO)
0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition).
1: ACBADDR[7] is set and the first 7 bits of the address byte (the first byte transferred after a Start Condition) match the 7-
BB (Bus Busy). (R/W1C)
0: Writing 1, ACB disabled, or Stop Condition detected.
1: Bus active (a low level on either ABD or ABC), or Start Condition.
BUSY. (RO) This bit should always be written 0. This bit indicates the period between detecting a Start Condition and com-
pleting receipt of the address byte. After this, the ACB is either free or enters slave mode.
0: Completion of any state below or ACB disabled.
1: ACB is in one of the following states:
STASTRE (Stall After Start Enable).
0: When cleared, ACBST[3] can not be set. However, if ACBST[3] is set, clearing STASTRE does not clear ACBST[3].
1: Stall after start mechanism enabled, and ACB stalls the bus after the address byte.
NMINTE (New Match Interrupt Enable).
0: No interrupt issued on a new match.
1: Interrupt issued on a new match only if ACBCTL1[2] set.
GCMEN (Global Call Match Enable).
0: Global call match disabled.
1: Global call match enabled.
ACK (Acknowledge). This bit is ignored in transmit mode. When the device acts as a receiver (slave or master), this bit
holds the stop transmitting instruction that is transmitted during the next acknowledge cycle.
0: Cleared after acknowledge cycle.
1: Negative acknowledge issued on next received byte.
Reserved.
is ignored.
bit address in ACBADDR.
-Generating a Start Condition
-Master mode (ACBST[1] is set)
-Slave mode (ACBCST[2] or ACBCST[3] set).
(Continued)
Table 4-32.
ACB Control Status Register - ACBCST (R/W)
ACB Control Register 1 - ACBCTL1 (R/W)
ACB Registers (Continued)
136
Reset Value: 00h
Reset Value: 00h
Revision 3.0