SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 292

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
Offset 0Ch-0Fh
Note:
Offset 10h-13h
Note:
29:7
29:7
Bit
31
30
31
30
6
5
4
3
2
1
0
6
5
4
3
2
1
0
All bits are set by hardware and cleared by software.
Writing a 1 to a bit in this register sets the corresponding bit, while writing a 0 leaves the bit unchanged.
Description
Reserved. Read/Write 0s.
OwnershipChange. This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set.
Reserved. Read/Write 0s.
RootHubStatusChange. This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has
changed.
FrameNumberOverflow. Set when bit 15 of FrameNumber changes value.
UnrecoverableError (Read Only). This event is not implemented and is hard-coded to 0. Writes are ignored.
ResumeDetected. Set when HC detects resume signaling on a downstream port.
StartOfFrame. Set when the Frame Management block signals a Start of Frame event.
WritebackDoneHead. Set after the HC has written HcDoneHead to HccaDoneHead.
SchedulingOverrun. Set when the List Processor determines a Schedule Overrun has occurred.
MasterInterruptEnable. This bit is a global interrupt enable. A write of 1 allows interrupts to be enabled via the specific
enable bits listed above.
OwnershipChangeEnable.
0: Ignore.
1: Enable interrupt generation due to Ownership Change.
Reserved. Read/Write 0s.
RootHubStatusChangeEnable.
0: Ignore.
1: Enable interrupt generation due to Root Hub Status Change.
FrameNumberOverflowEnable.
0: Ignore.
1: Enable interrupt generation due to Frame Number Overflow.
UnrecoverableErrorEnable. This event is not implemented. All writes to this bit are ignored.
ResumeDetectedEnable.
0: Ignore.
1: Enable interrupt generation due to Resume Detected.
StartOfFrameEnable.
0: Ignore.
1: Enable interrupt generation due to Start of Frame.
WritebackDoneHeadEnable.
0: Ignore.
1: Enable interrupt generation due to Writeback Done Head.
SchedulingOverrunEnable.
0: Ignore.
1: Enable interrupt generation due to Scheduling Overrun.
Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
(Continued)
HcInterruptEnable Register (R/W)
HcInterruptStatus Register (R/W)
292
Reset Value = 00000000h
Reset Value = 00000000h
Revision 3.0