SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 95

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
General Configuration Block
3.5.2
The core clock is generated by an Analog Delay Loop
(ADL) clock generator from the internal Fast-PCI clock. The
clock can be any whole-number multiple of the input clock
between 4 and 10. Possible values are listed in Table 3-6.
At power-on reset, the core clock multiplier value is set
according to the value of four strapped balls - CLKSEL[3:0]
(EBGA balls AL13, AK3, B27, F3 / TEPBGA balls P30,
D29, AF3, B8). These balls also select the clock which is
used as input to the multiplier, as shown in Table 3-7.
3.5.3
The internal Fast-PCI clock can be configured to 33, 48, or
66 MHz via strap options on the CLKSEL1 and CLKSEL0
balls. These can be read in the internal Fast-PCI Clock field
in the CCFC register (GCB+I/O Offset 1Eh[9:8]). (See
Table 3-2 on page 81 details on the CCFC register.)
CLKSEL[3:0]
Straps
0111
1011
1111
0000
0100
1000
1100
0001
0101
1001
1101
0110
1010
GX1 Module Core Clock
Internal Fast-PCI Clock
(GCB+I/O Offset 1Eh[9:8])
Internal Fast-PCI Clock
Freq. (MHz)
33.33
66.67
48
Table 3-7. Strapped Core Clock Frequency
(Continued)
Multiply By
10
4
5
6
7
8
9
4
5
6
7
4
5
95
Default ADL Multiplier
Multiplier
Value
ADL
(GCB+I/O Offset 1Eh[3:0])
10
4
5
6
7
8
9
Table 3-6. Core Clock Frequency
Multiplier Value
0100
0101
0110
0111
1000
1001
1010
0100
0101
0110
0111
0100
0101
Internal Fast-PCI Clock Freq. (MHz)
33.33
133.3
166.7
233.3
266.7
200
300
---
192
240
288
48
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Clock Freq. (MHz)
Maximum Core
Reserved
Reserved
Reserved
133
167
200
233
267
300
192
240
288
267
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66.67
266.7
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