SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 164

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
5.2.6.3
The Core Logic module contains two 8259A-equivalent
programmable interrupt controllers, with eight interrupt
request lines each, for a total of 16 interrupts. The two con-
trollers are cascaded internally, and two of the interrupt
request inputs are connected to the internal circuitry. This
allows a total of 13 externally available interrupt requests.
See Figure 5-9.
Each Core Logic IRQ signal can be individually selected to
as edge- or level-sensitive. The four PCI interrupt signals
may be routed internally to any PIC IRQ.
.
Three interrupts are available externally depending upon
selected ball multiplexing:
1)
2)
3)
More of the IRQs are available through the use of SERIRQ
(muxed with GPIO39) function. See Table 5-4.
RTC_IRQ#
8254 Timer 0
IRQ14 (muxed with TFTD1), and
IRQ9 (muxed with IDE_DATA6)
IRQ15 (muxed with GPIO11+RI2#),
Figure 5-8. PIC Interrupt Controllers
Programmable Interrupt Controller
FPU
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8#
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
(Continued)
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
Internal
INTR
164
The Core Logic module allows PCI interrupt signals INTA#,
INTB#, INTC# (muxed with GPIO19+IOCHRDY) and
INTD# (muxed with IDE_DATA7) to be routed internally to
any IRQ signal. The routing can be modified through Core
Logic module’s configuration registers. If this is done, the
IRQ input must be configured to be level- rather than edge-
sensitive. IRQ inputs may be individually programmed to be
active low, level-sensitive with the Interrupt Sensitivity con-
figuration registers at I/O address space 4D0h and 4D1h.
PCI interrupt configuration is discussed in further detail in
“PCI Compatible Interrupts” on page 165.
Master
IRQ
IRQ0
IRQ2
IRQ8#
IRQ13
IRQ15
IRQ14
IRQ12
IRQ11
IRQ10
IRQ9
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ1
Table 5-4. PIC Interrupt Mapping
Mapping
Connected to the OUT0 (system timer) of
the internal 8254 PIT.
Connected to the slave’s INTR for a cas-
caded configuration.
Connected to internal RTC.
Connected to the FPU interface of the
GX1 module.
Interrupts available to other functions
Revision 3.0