SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 321

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Video Processor Module
Weave
The Weave method assembles the odd field and even field
together to form the complete frame, and then renders the
“weaved” frames to the display device. The Video data is
converted from interlaced to progressive. Since both fields
are rendered simultaneously, the GX1 module’s video
frame buffer must be at least double buffered. The Weave
method has the advantage of not creating the temporal
effects that Bob does. The disadvantage of Weave is twice
as much data is transferred from the video frame buffer to
the Video Processor; meaning that Weave uses more
memory bandwidth.
Figure 6-6 on page 322 is an example of the Weave
method in action. As in the Bob example (Figure 6-5), a
CRT monitor at 85 Hz refresh is assumed. Double buffering
of the incoming data is also assumed. The example does
not assume anything about any scaling that may be done in
the Video Processor. No attempt has been made to assure
that this example is absolutely workable. The example is
only presented to allow for a general understanding of how
the SC2200’s video support hardware works.
The following procedure is an example of how to create the
Weave method. Since at least double buffering is required,
more of the VIP’s control registers are used for Weave than
required for Bob during video runtime.
(F4BAR2+Memory Offset 20h)
85 frames per second
Video subsystem
Capture video fill
empty sequence
Video Data Odd Base
Address not changed
sequence
Figure 6-5. Capture Video Mode Bob Example Using One Video Frame Buffer
during runtime
30 frames per second
Buf #1
1
(Continued)
1
2
Field
Odd
2
3
3
4
4
5
5
5
Ping-pongs between the two buffers during runtime
6
6
7
321
Address not changed during runtime
(GX_BASE+Memory Offset 8320h)
GX1 Module’s Video Frame Buffer
7
8
(F4BAR2+Memory Offset 24h)
1)
2)
9 10 11 12 13 14 15 16 17 18 19 20
8
Video Data Even Base
DC_VID_ST_OFFSET
Program the VIP bus master address registers.
Three registers control where the VIP video data is
stored in the GX1 module’s frame buffer:
The Video Data Even Base Address must be sepa-
rated from the Video Data Odd Base Address by one
horizontal line. The Video Data Pitch register must be
programmed to one horizontal line.
Program other VIP bus master support registers.
Ensure the VIP FIFO Bus Request Threshold is set to
32 bytes (F4BAR2+Memory Offset 00h[22] = 1) and
the Video Input Port mode is set to CCIR-656
(F4BAR2+Memory Offset 00h[1:0] = 10). An interrupt
needs to be generated so that the GX1 module’s video
frame buffer pointer can flip to the field that has com-
pleted transfer to the video frame buffer. So the Field
Interrupt bit (F4BAR2+Memory Offset 04h[16] = 1).
must
(F4BAR2+Memory Offset 04h[10] = 0) to allow the
CCIR-656 decoder to identify which field is being pro-
cessed. Capture video data needs to be enabled
(F4BAR2+Memory Offset 04h[10] = 1) and Run Mode
Capture is set to Start Capture (F4BAR2+Memory Off-
set 04h[1:0] = 11) at beginning of next field. Data is
now being captured to the frame buffer.
– F4BAR2+Memory Offset 20h – Video Data Odd
– F4BAR2+Memory Offset 24h – Video Data Even
– F4BAR2+Memory Offset 28h – Video Data Pitch
9
Base Address
Base Address
10
be
11
enabled.
12
13
Auto-Flip
14
15
16
is
21
17
normally
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Even
Field
22 23
set