SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 209

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Index 64h-6Dh
Index 6Eh-6Fh
Index 70h-71h
Index 72h
This register is used in conjunction with F0 Index 70h (IOCS1# Base Address register).
Index 73h
Index 74h-75h
15:8
15:0
15:0
7:4
3:0
4:0
Bit
1
0
7
6
5
Description
ACPI SL1 SUSP_3V Enable. Allow internal SUSP_3V to be active during SL1 sleep state.
0: Disable.
1: Enable.
ACPI C3 Support Enable. Allow support of C3 states.
0: Disable.
1: Enable.
Reserved. Must be set to FFh.
ROM Size. If F0 Index 52h[2] = 1:
0000: 16 MB = FF000000h-FFFFFFFFh
1000: 8 MB = FF800000h-FFFFFFFFh
1100: 4 MB = FFC00000h-FFFFFFFFh
1110: 2 MB = FFE00000h-FFFFFFFFh
1111: 1 MB = FFF00000h-FFFFFFFFh
All other settings for these bits are reserved.
Reserved. Must be set to 0.
I/O Chip Select 1 Base Address. This 16-bit value represents the I/O base address used to enable assertion of IOCS1#
(EBGA ball H2 or AL12 / TEPBGA ball D10 or N30 - see PMR[23] in Table 3-2 on page 81).
This register is used in conjunction with F0 Index 72h (IOCS1# Control register).
I/O Chip Select 1 Positive Decode (IOCS1#).
0: Disable.
1: Enable.
Writes Result in Chip Select. When this bit is set to 1, writes to configured I/O address (base address configured in F0
Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.
0: Disable.
1: Enable.
Reads Result in Chip Select. When this bit is set to 1, reads from configured I/O address (base address configured in F0
Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.
0: Disable.
1: Enable.
IOCS1# I/O Address Range. This 5-bit field is used to select the range of IOCS1#.
00000: 1 Byte
00001: 2 Bytes
00011: 4 Bytes
00111: 8 Bytes
I/O Chip Select 0 Base Address. This 16-bit value represents the I/O base address used to enable the assertion of
IOCS0# (EBGA ball J4 / TEPBGA ball A10 - see PMR[23] in Table 3-2 on page 81).
This register is used in conjunction with F0 Index 76h (IOCS0# Control register).
(Continued)
IOCS1# Base Address Register (R/W)
IOCS0# Base Address Register (R/W)
IOCS1# Control Register (R/W)
ROM Mask Register (R/W)
01111: 16 Bytes
11111: 32 Bytes
All other combinations are reserved.
Reserved
Reserved
209
Reset Value: FFF0h
Reset Value: 0000h
Reset Value: 0000h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
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