SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 254

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
Offset 08h-09h
Notes: 1. This is the top level of PME/SCI status reporting for these events. There is no second level.
14:12
7:6
Bit
15
11
10
0
9
8
5
2. If SCI generation is not desired, the status bits are still set by the described conditions and can be used for monitoring pur-
Description
PWRBTN_DBNC_DIS (Power Button Debouncer). Allow a high-to-low or low-to-high transition of greater than 15.8 msec
(debounce period) on PWRBTN# before it is recognized.
0: Enable. (Default)
1: Disable.
WAK_STS (Wakeup Status). Indicates whether or not an SCI was caused by the occurrence of an enabled wakeup event.
0: No.
1: Yes.
This bit is set when the system is in any Sleep state and an enabled wakeup event occurs (wakeup events are configured at
F1BAR1+I/O Offset 0Ah and 12h). After this bit is set, the system transitions to a Working state.
SCI generation is always enabled.
Write 1 to clear.
Reserved. Must be set to 0.
PWRBTNOR_STS (Power Button Override Status). Indicates whether or not an SCI was caused by the power button
being active for greater than 4 seconds.
0: No.
1: Yes.
SCI generation is always enabled.
Write 1 to clear.
RTC_STS (Real-Time Clock Status). Indicates if a Power Management Event (PME) was caused by the RTC generating
an alarm (RTC IRQ signal is asserted).
0: No.
1: Yes.
For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ah[10] to 1 and F1BAR1+I/O Offset 0Ch[0] to 1. (See Note 2 in
the general description of this register.)
Write 1 to clear.
Reserved. Must be set to 0.
PWRBTN_STS (Power Button Status). Indicates if PME was caused by the PWRBTN# going low while the system is in a
Working state.
0: No.
1: Yes.
For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ah[8] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the
general description of this register.)
In a Sleep state or the Soft-Off state, a wakeup event is generated when the power button is pressed (regardless of the
PWRBTN_EN bit, F1BAR1+I/O Offset 0Ah[8], setting).
Write 1 to clear.
Reserved. Must be set to 0.
GBL_STS (Global Lock Status). Indicates if PME was caused by the BIOS releasing control of the global lock.
0: No.
1: Yes.
This bit is used by the BIOS to generate an SCI. BIOS writes the BIOS_RLS bit (F1BAR1+I/O Offset 0Fh[1]) which in turns
sets the GBL_STS bit and raises a PME.
For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ah[5] to 1 and F1BAR1+I/O Offset 0Ch[0] to 1. (See Note 2 in the
general description of this register.)
Write 1 to clear.
poses.
Table 5-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)
(Continued)
PM1A_STS — PM1A Top Level PME/SCI Status Register (R/W)
254
Reset Value: 0000h
Revision 3.0