SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 313

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Core Logic Module
I/O Port 070h
This register is shadowed within the Core Logic module and is read through the RTC Shadow Register (F0 Index BBh).
I/O Port 071h
A read of this register returns the value of the register indexed by the RTC Address Register.
A write of this register sets the value into the register indexed by the RTC Address Register
I/O Port 072h
I/O Port 073h
AA read of this register returns the value of the register indexed by the RTC Extended Address Register.
A write of this register sets the value into the register indexed by the RTC Extended Address Register
I/O Port 0F0h, 0F1h
A write to either port when the internal FERR# signal is asserted causes the Core Logic Module to assert internal IGNNE#. IGNNE#
remains asserted until the FERR# deasserts.
I/O Ports 170h-177h/376h-377h
When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according
to their configuration rather than generating standard ISA bus cycles.
I/O Ports 1F0h-1F7h/3F6h-3F7h
When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according
to their configuration rather than generating standard ISA bus cycles.
I/O Port 4D0h
Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides the setting for bits [7:3] in this register.
6:0
6:0
Bit
Bit
7
7
7
6
5
4
2. Bits [7:3] in this register are used to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared).
Description
NMI Mask.
0: Enable.
1: Mask.
RTC Register Index. A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered.
(RTCALE is an internal signal between the Core Logic module and the internal RTC controller.)
Reserved.
RTC Register Index. A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered.
(RTCALE is an internal signal between the Core Logic module and the internal RTC controller.)
Description
IRQ7 Edge or Level Sensitive Select. Selects PIC IRQ7 sensitivity configuration.
0: Edge.
1: Level.
IRQ6 Edge or Level Sensitive Select. Selects PIC IRQ6 sensitivity configuration.
0: Edge.
1: Level.
IRQ5 Edge or Level Sensitive Select. Selects PIC IRQ5 sensitivity configuration.
0: Edge.
1: Level.
IRQ4 Edge or Level Sensitive Select. Selects PIC IRQ4 sensitivity configuration.
0: Edge.
1: Level.
(Continued)
Table 5-48. Real-Time Clock Registers
Interrupt Edge/Level Select Register 1 (R/W)
Table 5-49. Miscellaneous Registers
RTC Extended Address Register (WO)
Coprocessor Error Register (W)
Secondary IDE Registers (R/W)
Primary IDE Registers (R/W)
RTC Address Register (WO)
RTC Data Register (R/W)
RTC Data Register (R/W)
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Reset Value: F0h
Reset Value: 00h
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