SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 51

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Signal Definitions
2.2
Several balls are read at power-up that set up the state of
the SC2200. These balls are typically multiplexed with
other functions that are outputs after the power-up
sequence is complete. The SC2200 must read the state of
the balls at power-up and the internal PU or PD resistors
do not guarantee the correct state will be read. Therefore, it
is required that an external PU or PD resistor with a value
Strap
Option
CLKSEL0
CLKSEL1
CLKSEL2
CLKSEL3
BOOT16
TFT_PRSNT
LPC_ROM
FPCI_MON
DID0
DID1
Note: Accuracy of internal PU/PD resistors: 80K to 250K.
STRAP OPTIONS
Location of the GCB (General Configuration Block) cannot be determined by software. See the SC2200 Thin Client On a Chip
device errata document.
Muxed With
RD#
SOUT1
SOUT2
SYNC
ROMCS#
SDATA_OUT
PCICLK1
PCICLK0
GNT0#
GNT1#
(Continued)
EBGA
AK13
AL13
B27
AK3
G4
F3
E4
D3
D4
D2
Ball No.
TEPBGA
AF3
D29
P30
P29
B8
C8
D6
A4
C5
C6
Table 2-6. Strap Options
PU or PD
Nominal
Internal
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
100
100
100
100
100
100
100
100
100
100
See Table 3-7 on page 95 for
CLKSEL strap options.
Enable boot
from 8-bit ROM
TFT not muxed
onto Parallel
Port
Disable boot
from ROM on
LPC bus
Disable Fast-
PCI, INTR_O,
and SMI_O
monitoring sig-
nals.
Defines the system-level chip ID.
51
Strap = 0 (PD)
External PU/PD Strap Settings
of 1.5 K
value of the resistor is important to ensure that the proper
state is read during the power-up sequence. If the ball is
not read correctly at power-up, the SC2200 may default to
a state that causes it to function improperly, possibly result-
ing in application failure.
be placed on the balls listed in Table 2-6. The
Enable boot
from 16-bit
ROM
TFT muxed
onto Parallel
Port
Enable boot
from ROM on
LPC bus
Enable Fast-
PCI, INTR_O,
and SMI_O
monitoring sig-
nals. (Useful
during debug.)
Strap = 1 (PU)
Register References
GCB+I/O Offset 1Eh[9:8] (aka
CCFC register bits [9:8]) (RO):
Value programmed at reset by
CLKSEL[1:0].
GCB+I/O Offset 10h[3:0] (aka
MCCM register bits [3:0]) (RO):
Value programmed at reset by
CLKSEL[3:0].
GCB+I/O Offset 1Eh[3:0] (aka
CCFC register bits [3:0]) (R/W,
but write not recommended):
Value programmed at reset by
CLKSEL[3:0].
Note: Values for GCB+I/O Offset
10h[3:0] and 1Eh[3:0] are not the
same.
GCB+I/O Offset 34h[3] (aka MCR
register bit 3) (RO): Reads back
strap setting.
GCB+I/O Offset 34h[14] (R/W):
Used to allow the ROMCS# width
to be changed under program
control.
GCB+I/O Offset 30h[23] (aka
PMR register bit 23) (R/W):
Reads back strap setting.
F0BAR1+I/O Offset 10h[15]
(R/W): Reads back strap setting
and allows LPC ROM to be
changed under program control.
GCB+I/O Offset 34h[30] (aka
MCR register bit 30) (RO): Reads
back strap setting.
Note: For
GCB+I/O Offset 34h[31,29] (aka
MCR register bits 31 and 29)
(RO): Reads back strap setting.
Note:
strap this signal low using
a 1.5 K
GNT0# must have a PU
resistor of 1.5 K
GNT1# must have a PD
resistor of 1.5 K .
normal
resistor.
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operation,
and