SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 225

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Index BAh
Index BBh
Index BCh
Note:
Index BDh-BFh
Index C0h-C3h
31:0
7:0
7:0
7:4
3:1
Bit
0
This register configures the Core Logic module to support a 3V Suspend mode. Setting bit 0 causes the SUSP_3V signal to
assert after the appropriate conditions, stopping the system clocks. A delay of 0-15 msec is programmable (bits [7:4]) to allow
for a delay for the clock chip and CPU PLL to stabilize when an event Resumes the system.
A write to the CPU Suspend Command register (F0 Index AEh) with bit 0 written as:
0: Internal SUSP#/SUSPA# handshake occurs. The GX1 module is put into a low-power state, and the system clocks are not
stopped. When a break/resume event occurs, it releases the CPU halt condition.
1: Internal SUSP#/SUSPA# handshake occurs and the SUSP_3V signal is asserted, thus invoking a full system Suspend (both
GX1 module and system clocks are stopped). When a break event occurs, the SUSP_3V signal is deasserted, the PLL delay
programmed in bits [7:4] are invoked which allows the clock chip and GX1 module PLL to stabilize before deasserting the inter-
nal SUSP# signal.
Description
PIT Shadow. This 8-bit port sequences through the following list of shadowed Programmable Interval Timer registers. At
power on, a pointer starts at the first register in the list and continuing through the other registers in subsequent reads
according to the read sequence. A write to this register resets the read sequence to the first register. Each shadow register
in the sequence contains the last data written to that location.
The read sequence for this register is:
1. Counter 0 LSB (least significant byte)
2. Counter 0 MSB
3. Counter 1 LSB
4. Counter 1 MSB
5. Counter 2 LSB
6. Counter 2 MSB
7. Counter 0 Command Word
8. Counter 1 Command Word
9. Counter 2 Command Word
Note:
RTC Index Shadow. The RTC Shadow register contains the last written value of the RTC Index register (I/O Port 070h).
PLL Delay. The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the internal
SUSP# signal is deasserted to the GX1 module. This delay is designed to allow the clock chip and CPU PLL to stabilize
before starting execution. This delay is only invoked if the STP_CLK bit was set.
The 4-bit field allows values from 0 to 15 msec.
0000: 0 msec
0001: 1 msec
0010: 2 msec
0011: 3 msec
Reserved. Set to 0.
CPU Clock Stop.
0: Normal internal SUSP#/SUSPA# handshake.
1: Full system Suspend.
User Defined Device 1 Base Address. This 32-bit register supports power management (Trap and Idle timer resources) for
a PCMCIA slot or some other device in the system. The value in this register is used as the address comparator for the
device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh).
The Core Logic module cannot snoop addresses on the Fast-PCI bus unless it actually claims the cycle. Therefore, Traps
and Idle timers cannot support power management of devices on the Fast-PCI bus.
The LSB/MSB of the count is the Counter base value, not the current value.
Bits [7:6] of the command words are not used.
(Continued)
User Defined Device 1 Base Address Register (R/W)
0100: 4 msec
0101: 5 msec
0110: 6 msec
0111: 7 msec
Clock Stop Control Register (R/W)
RTC Index Shadow Register (RO)
PIT Shadow Register (RO)
Reserved
225
1000: 8 msec
1001: 9 msec
1010: 10 msec
1011: 11 msec
1100: 12 msec
1101: 13 msec
1110: 14 msec
1111: 15 msec
Reset Value: 00000000h
Reset Value: xxh
Reset Value: xxh
Reset Value: 00h
Reset Value: 00h
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