h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 499

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and
data is transferred with LSB-first as the start character, as shown in figure 16.26. Therefore, data
in the start character in the figure is H'3B. When using the direct convention type, write 0 to both
the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity,
which is prescribed by the smart card standard.
For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively
and data is transferred with MSB-first as the start character, as shown in figure 16.27. Therefore,
data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to
both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity,
which is prescribed by the smart card standard, and corresponds to state Z. Since the SNIV bit of
this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in
both transmission and reception.
16.7.3
Block transfer mode is different from normal smart card interface mode in the following respects.
16.7.4
Only the internal clock generated by the internal baud rate generator can be used as a
communication clock in smart card interface mode. In this mode, the SCI can operate using a basic
clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0
settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At
reception, the falling edge of the start bit is sampled using the internal basic clock in order to
perform internal synchronization. Receive data is sampled at the 16th, 32nd, 186th and 128th
If a parity error is detected during reception, no error signal is output. Since the PER bit in SSR
is set by error detection, clear the bit before receiving the parity bit of the next frame.
During transmission, at least 1 etu is secured as a guard time after the end of the parity bit
before the start of the next frame.
Since the same data is not re-transmitted during transmission, the TEND flag in SSR is set 11.5
etu after transmission start.
Although the ERS flag in block transfer mode displays the error signal status as in normal
smart card interface mode, the flag is always read as 0 because no error signal is transferred.
Block Transfer Mode
Receive Data Sampling Timing and Reception Margin
(Z)
Figure 16.27 Inverse Convention (SDIR = SINV = O/E E E E = 1)
Ds
A
D7
Z
D6
Z
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
D5
A
D4
A
D3
A
D2
A
D1
A
Rev. 3.00 Jan 25, 2006 page 447 of 872
D0
A
Dp
Z
(Z) state
REJ09B0286-0300