h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 594

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 17 I
5. The I
Table 17.12 Permissible SCL Rise Time (t
6. The I
Rev. 3.00 Jan 25, 2006 page 542 of 872
REJ09B0286-0300
IICX1,
IICX0
0
1
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 17.12.
and 300 ns. The I
in table 17.11. However, because of the rise and fall times, the I
may not be satisfied at the maximum transfer rate. Table 17.13 shows output timing
calculations for different operating frequencies, including the worst-case influence of rise and
fall times. The values in the above table will vary depending on the settings of the IICX1,
IICX0, and CKS2 to CKS0 bits. Depending on the frequency it may not be possible to achieve
the maximum transfer rate; therefore, whether or not the I
met must be determined in accordance with the actual setting conditions. t
I
investigated.
•
•
•
•
2
C bus interface specifications at any frequency. The following solutions should be
t
Indication
7.5 t
17.5 t
Provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition.
Select devices whose input timing permits this output timing for use as slave devices
connected to the I
t
specifications for worst-case calculations of t
investigated.
Adjusting the rise and fall times by means of a pull-up resistor and capacitive load.
Reducing the transfer rate to meet the specifications.
cyc
SCLLO
2
2
C bus interface specification for the SCL rise time t
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
cyc
cyc
2
in high-speed mode and t
C Bus Interface (IIC)
Standard mode
High-speed mode 300
Standard mode
High-speed mode 300
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus.
I
Specification
(Max.)
1000
1000
2
C Bus
2
STASO
C bus interface monitors the SCL line and synchronizes
in standard mode fail to satisfy the I
sr
) Values
sr
(the time for SCL to go from low to V
5 MHz
1000
300
1000
300
2
C bus interface, the high period of SCL is
=
Sr
/t
Sf
. The following solutions should be
8 MHz
937
300
1000
300
Time Indication[ns]
=
sr
2
C bus interface specifications are
is 1000 ns or less (300 ns for high-
10 MHz
750
300
1000
300
=
2
C bus interface specifications
16 MHz
468
300
1000
300
=
BUFO
2
20 MHz
375
300
875
300
C bus interface
fails to meet the
=
cyc
, as shown
IH
) exceeds
25 MHz
300
300
700
300
=