h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 696

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 19 Multimedia Card Interface (MCIF)
19.3.11 Data Timeout Register (DTOUTR)
DTOUTR specifies the cycle to generate a data timeout. The 16-bit counter (DTOUTC) and a
prescaler, to which the CPU does not have access, count the system clock to monitor the data
timeout. The prescaler always counts the system clock, and outputs a count pulse for every 10000
system clocks. The DTOUTC starts counting the prescaler output from the start of the command
sequence. The DTOUTC is cleared when the command sequence has ended, or when the
command sequence has been aborted by setting the CMDOFF bit to 1, after which the DTOUTC
stops counting the prescaler output.
When the command sequence does not end, the DTOUTC continues counting the prescaler output,
and enters the data timeout error state when the number of prescaler outputs reaches the number
specified in DTOUTR. When the DTERIE bit in INTCR1 is set to 1, the DTERI flag in INTSTR1
is set. As the DTOUTC continues counting prescaler output, the DTERI flag setting condition is
repeatedly generated. To perform data timeout error handling, the command sequence should be
aborted by setting the CMDOFF bit to 1, and then the DTERI flag should be cleared to prevent
extra-interrupt generation.
For a command with data busy status, as the command sequence is terminated before entering the
data busy state, data timeout cannot be monitored. Timeout in the data busy state should be
monitored by firmware.
Rev. 3.00 Jan 25, 2006 page 644 of 872
REJ09B0286-0300
Bit
7
to
1
0
Bit
15
to
0
Bit Name
—
CTSEL0
Bit Name
—
Initial Value
All 0
0
Initial Value
All 1
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Command Timeout Select Specifies the number
of transfer clocks from command transmission
completion to response reception completion.
0: 128 transfer clocks
1: 256 transfer clocks
Description
Data Timeout Time/10000
Data timeout time can be obtained by system
clock cycle
DTOUTR setting value
10000.