h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 671

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Reset State: A reset state is entered by bringing the RES pin of the LSI to low. In a reset state,
registers that can be initialized and the internal status of the LSI are initialized and all pins of the
LSI are placed in input state.
XTAL-EXTAL system clock oscillation can be continued in the clock pulse generator.
Module Stop Mode: The USB module enters module stop mode when the SMSTPB1 bit in
subchip module stop control register BL (SUBMSTPBL) is set to 1. In a module stop mode, the
system clock supply to the USB module stops. Note that supply of the USB operating clock (48
MHz) does not stop so, the USB module continues operation. To place the USB module in a
module stop mode, initialize the USBCR1 and UPLLCR. In addition, it is recommended that
USBCR0 should be initialized to prepare a module stop mode cancellation. Since the module stop
bit of SUBMSTPCR is initialized to 1 in hardware standby mode or by a reset, the USB module is
placed in a module stop mode after reset cancellation.
Software Standby Mode: Software standby mode is entered if the SLEEP instruction is executed
while the SSBY bit of SBYCR is set to 1. In software standby mode, the USB module is not
placed in a reset or operation stop state. Note that if the slave CPU stops operation in software
standby mode, the USB function core operation may not be performed completely. To specify
software standby mode regardless of the host status, set the UIFRST, FPLLRST, and FSRST bits
of USBCR0 to 1 to stop the USB module operation before software standby mode is entered. Due
to this, the registers shown in table 18.6 are initialized. In this case, external pull-up MOSs must
be specified to be in a cable disconnected state.
These descriptions also apply to watch mode, subactive mode, and subsleep mode.
Table 18.6 Registers Initialized by Bit UIFRST or FSRST
When the host enters a suspend state, software standby mode in which the host waits for
cancellation (resume) can be specified.
Register Name
EPDR3, EPDR2, EPDR1, EPDR0S, EPDR0O, EPDR0I
FVSR3, FVSR2, FVSR1, FVSR0S, FVSR0O, FVSR0I
EPSZR1
USBIER0, USBIER1
USBIFR0, USBIFR1, TSFR0, TFFR0, UDTRFR, CONFV
USBCSR0, DEVRSMR, EPSTLR0
EPDIR0
INTSELR0, EP4PKTSZR, USBMDCR
Section 18 Universal Serial Bus Interface (USB)
Rev. 3.00 Jan 25, 2006 page 619 of 872
UIFRST/FSRST
FSRST
FSRST
UIFRST
UIFRST
FSRST
FSRST
UIFRST
UIFRST
REJ09B0286-0300