h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 673

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

18.4.7
USB Module Configuration: The USB module is comprised of several components. To correctly
operate these components and notify the host, the USB module must be started up by the firmware
(this LSI’s program) according to the sequence described later.
The USB module is comprised of:
(a) USB clock external input pin, USB operating clock PLL circuit
(b) USB bus clock synchronization DPLL (12 MHz)
USB clock external input pin, USB operating clock PLL (48 MHz)
USB bus clock synchronization DPLL (12 MHz)
EPINFO: Endpoint information
Slave CPU, core interface
USB function core
The PLL circuit that generates the USB operating clock multiplies the clock input from the
USB clock external input pin or the oscillator to generate a 48-MHz clock. Therefore, the
clock input to the PLL circuit must be 8, 12, 16, 20, or 24 MHz. The multiplication rate of the
PLL circuit can be specified by the PFSEL bit in UPLLCR. The 48-MHz clock generated by
the PLL circuit can be divided to generate a 24-MHz clock. This 24-MHz clock can be used as
the system clock.
For USB operation clock PLL stabilization time, set the UIFRST, PFLLRST, and FSRST bits
of the USBCR0 to 1 to place the USB bus clock synchronization DPLL and USB function core
in a reset state.
The USB data is transferred at 12 Mbps (maximum). The bit data is sampled at the timing
using the 48-MHz USB operating clock and the phase is adjusted while the synchronization
pattern is received prior to the packet. This mechanism is called the USB bus clock
synchronization DPLL.
The USB bus clock synchronization DPLL stabilization time is defined by firmware. For the
USB bus clock synchronization DPLL stabilization time, set the FSRST bit of USBCR0 to 1 to
place the USB function core in a reset state.
It is recommended that the USB bus clock synchronization DPLL stabilization time should be
10 cycles or more in a 48-MHz clock.
USB Module Startup Sequence
Section 18 Universal Serial Bus Interface (USB)
Rev. 3.00 Jan 25, 2006 page 621 of 872
REJ09B0286-0300